mc68hc08ln56 Freescale Semiconductor, Inc, mc68hc08ln56 Datasheet - Page 208

• Manufacturer Part Number: mc68hc08ln56
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Computer Operating Properly Module (COP)
The COP counter is a free-running 6-bit counter preceded by the 13-bit system integration module (SIM)
counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after
2
value to location $FFFF before overflow occurs clears the COP counter and prevents reset.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the COP bit in the SIM reset status
register (SRSR) (See SIM section for more details). Clear the COP immediately before entering or after
exiting stop mode to assure a full COP timeout period after entering or exiting stop mode. A CPU interrupt
routine or a DMA service routine can be used to clear the COP.
16.3 I/O Signals
The following paragraphs describe the signals shown in
16.3.1 CGMXCLK
CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency is equal to the crystal frequency.
16.3.2 STOP Instruction
The STOP instruction clears the SIM counter.
16.3.3 COPCTL Write
Writing any value to the COP control register (COPCTL) (See
clears the COP counter and clears bits 12 through 4 of the SIM counter. Reading the COP control register
returns the reset vector.
16.3.4 Power-On Reset
The power-on reset (POR) circuit in the SIM clears the SIM counter 4096 CGMXCLK cycles after
power-up.
16.3.5 Internal Reset
An internal reset clears the SIM counter and the COP counter.
16.3.6 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears
the SIM counter.
16.3.7 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the mask option register (MOR).
(See
208
18
– 2
Chapter 19 Configuration Register (CONFIG)
4
CGMXCLK cycles. With a 4.9152-MHz crystal, the COP timeout period is 53.3 ms. Writing any
Place COP clearing instructions in the main program and not in an interrupt
subroutine. Such an interrupt subroutine could keep the COP from
generating a reset even while the main program is not working properly.
MC68HC08LN56 • MC68HC708LN56 General Release Specification, Rev. 2.1
NOTE
for more details.)
Figure
16.4 COP Control Register
16-1.
Freescale Semiconductor
(COPCTL))