mc68hc08ln56 Freescale Semiconductor, Inc, mc68hc08ln56 Datasheet - Page 161

• Manufacturer Part Number: mc68hc08ln56
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

RPF — Reception in Progress Flag Bit
12.8.6 SCI Data Register (SCDR)
The SCI data register is the buffer between the internal data bus and the receive and transmit shift
registers. Reset has no effect on data in the SCI data register.
R7/T7:R0/T0 — Receive/Transmit Data Bits
12.8.7 SCI Baud Rate Register (SCBR)
The baud rate register selects the baud rate for both the receiver and the transmitter.
SCP1 and SCP0 — SCI Baud Rate Prescaler Bits
Freescale Semiconductor
This read-only bit is set when the receiver detects a logic zero during the RT1 time period of the start
bit search. RPF does not generate an interrupt request. RPF is reset after the receiver detects false
start bits (usually from noise or a baud rate mismatch) or when the receiver detects an idle character.
Polling RPF before disabling the SCI module or entering stop mode can show whether a reception is
in progress.
Reading address $0018 accesses the read-only received data bits, R7:R0. Writing to address $0018
writes the data to be transmitted, T7:T0. Reset has no effect on the SCI data register.
These read/write bits select the baud rate prescaler divisor as shown in
and SCP0.
1 = Reception in progress
0 = No reception in progress
SCDR
$0018
SCBR
$0019
Reset:
Do not use read modify write instructions on the SCI data register.
Reset:
Read:
Write:
Read:
Write:
MC68HC08LN56 • MC68HC708LN56 General Release Specification, Rev. 2.1
Bit 7
Bit 7
R7
T7
0
Figure 12-18. SCI Baud Rate Register (SCBR)
= Unimplemented
Figure 12-17. SCI Data Register (SCDR)
R6
T6
6
6
0
SCP1
R5
T5
5
5
0
Unaffected by reset
NOTE
SCP0
R4
T4
4
4
0
R3
T3
R
R
3
3
0
= Reserved for Factory Test
SCR2
R2
T2
2
2
0
Table
SCR1
R1
T1
1
1
0
12-9. Reset clears SCP1
SCR0
Bit 0
Bit 0
R0
T0
0
I/O Registers
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