mc68hc08ln56 Freescale Semiconductor, Inc, mc68hc08ln56 Datasheet - Page 154

• Manufacturer Part Number: mc68hc08ln56
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Serial Communications Interface Module (SCI)
12.8.2 SCI Control Register 2 (SCC2)
SCI control register 2 does the following:
SCTIE — SCI Transmit Interrupt Enable Bit
TCIE — Transmission Complete Interrupt Enable Bit
SCRIE — SCI Receive Interrupt Enable Bit
ILIE — Idle Line Interrupt Enable Bit
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This read/write bit enables the SCTE bit to generate SCI transmitter CPU interrupt requests or DMA
service requests. Setting the SCTIE bit and clearing the DMA transfer enable bit, DMATE, in SCC3
enables the SCTE bit to generate CPU interrupt requests. Setting both the SCTIE and DMATE bits
enables the SCTE bit to generate DMA service requests. Reset clears the SCTIE bit.
This read/write bit enables the TC bit to generate SCI transmitter CPU interrupt requests. Reset clears
the TCIE bit.
This read/write bit enables the SCRF bit to generate SCI receiver CPU interrupt requests or SCI
receiver DMA service requests. Setting the SCRIE bit and clearing the DMA receive enable bit,
DMARE, in SCC3 enables the SCRF bit to generate CPU interrupt requests. Setting both SCRIE and
DMARE enables SCRF to generate DMA service requests. Reset clears the SCRIE bit.
This read/write bit enables the IDLE bit to generate SCI receiver CPU interrupt requests. Reset clears
the ILIE bit.
1 = SCTE enabled to generate CPU interrupt or DMA service requests
0 = SCTE not enabled to generate CPU interrupt or DMA service requests
1 = TC enabled to generate CPU interrupt requests
0 = TC not enabled to generate CPU interrupt requests
1 = SCRF enabled to generate CPU interrupt or DMA service requests
0 = SCRF not enabled to generate CPU interrupt or DMA service requests
1 = IDLE enabled to generate CPU interrupt requests
0 = IDLE not enabled to generate CPU interrupt requests
Enables the following CPU interrupt requests and DMA service requests:
–
–
–
–
Enables the transmitter
Enables the receiver
Enables SCI wake-up
Transmits SCI break characters
Enables the SCTE bit to generate transmitter CPU interrupt requests or transmitter DMA
service requests
Enables the TC bit to generate transmitter CPU interrupt requests
Enables the SCRF bit to generate receiver CPU interrupt requests or receiver DMA service
requests
Enables the IDLE bit to generate receiver CPU interrupt requests
$0014
SCC2
Reset:
Read:
Write:
MC68HC08LN56 • MC68HC708LN56 General Release Specification, Rev. 2.1
SCTIE
Bit 7
0
Figure 12-12. SCI Control Register 2 (SCC2)
TCIE
6
0
SCRIE
5
0
ILIE
4
0
TE
3
0
RE
2
0
RWU
1
0
Freescale Semiconductor
Bit 0
SBK
0