mc68hc08ln56 Freescale Semiconductor, Inc, mc68hc08ln56 Datasheet - Page 157

• Manufacturer Part Number: mc68hc08ln56
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

ORIE — Receiver Overrun Interrupt Enable Bit
NEIE — Receiver Noise Error Interrupt Enable Bit
FEIE — Receiver Framing Error Interrupt Enable Bit
PEIE — Receiver Parity Error Interrupt Enable Bit
12.8.4 SCI Status Register 1 (SCS1)
SCI status register 1 contains flags to signal these conditions:
Freescale Semiconductor
This read/write bit enables SCI error CPU interrupt requests generated by the receiver overrun bit, OR.
This read/write bit enables SCI error CPU interrupt requests generated by the noise error bit, NE.
Reset clears NEIE.
This read/write bit enables SCI error CPU interrupt requests generated by the framing error bit, FE.
Reset clears FEIE.
This read/write bit enables SCI receiver CPU interrupt requests generated by the parity error bit, PE.
(See
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1 = SCI error CPU interrupt requests from OR bit enabled
0 = SCI error CPU interrupt requests from OR bit disabled
1 = SCI error CPU interrupt requests from NE bit enabled
0 = SCI error CPU interrupt requests from NE bit disabled
1 = SCI error CPU interrupt requests from FE bit enabled
0 = SCI error CPU interrupt requests from FE bit disabled
1 = SCI error CPU interrupt requests from PE bit enabled
0 = SCI error CPU interrupt requests from PE bit disabled
Transfer of SCDR data to transmit shift register complete
Transmission complete
Transfer of receive shift register data to SCDR complete
Receiver input idle
Receiver overrun
Noisy data
Framing error
Parity error
12.8.4 SCI Status Register 1
$0016
SCS1
To enable the SCTE bit to generate DMA service requests, the SCI transmit
interrupt enable bit (SCTIE) must be set.
Reset:
Read:
Write:
MC68HC08LN56 • MC68HC708LN56 General Release Specification, Rev. 2.1
SCTE
Bit 7
1
Figure 12-14. SCI Status Register 1 (SCS1)
= Unimplemented
TC
6
1
(SCS1).) Reset clears PEIE.
SCRF
5
0
NOTE
IDLE
4
0
OR
3
0
NF
2
0
FE
1
0
Bit 0
PE
0
I/O Registers
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