mc68hc08ln56 Freescale Semiconductor, Inc, mc68hc08ln56 Datasheet - Page 174

• Manufacturer Part Number: mc68hc08ln56
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

I/O Ports
MOSI2 — Master Out/Slave In 2
MISO2 — Master In/Slave Out2
13.5.2 Data Direction Register D
Data direction register D determines whether each port D pin is an input or an output. Writing a logic one
to a DDRD bit enables the output buffer for the corresponding port D pin; a logic zero disables the output
buffer.
DDRD[7:0] — Data Direction Register D Bits
Figure 13-13
When bit DDRDx is a logic one, reading address $0003 reads the PTDx data latch. When bit DDRDx is
a logic zero, reading address $0003 reads the voltage level on the pin. The data latch can always be
174
The PTD6/MOSI2 pin is the master out/slave in terminal of the SPI2 module. When the SPE bit is clear,
the PTD6/MOSI2 pin is available for general-purpose I/O.
The PTD7/MISO2 pin is the master in/slave out terminal of the SPI2 module. When the SPI2 enable
bit, SPE2, is clear, the SPI2 module is disabled, and the PTD7/MISO2 pin is available for
general-purpose I/O.
These read/write bits control port D data direction. Reset clears DDRD[7:0], configuring all port D pins
as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
shows the port D I/O logic.
$000C
DDRD
Reset:
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Read:
Write:
MC68HC08LN56 • MC68HC708LN56 General Release Specification, Rev. 2.1
READ DDRD ($0007)
WRITE DDRD ($0007)
WRITE PTD ($0003)
READ PTD ($0003)
DDRD7
Bit 7
0
Figure 13-12. Data Direction Register D (DDRD)
DDRD6
6
0
RESET
Figure 13-13. Port D I/O Circuit
DDRD5
5
0
DDRD4
NOTE
DDRDx
PTDx
4
0
DDRD3
3
0
DDRD2
2
0
DDRD1
1
0
Freescale Semiconductor
DDRD0
Bit 0
0
PTDx