mc68hc08ln56 Freescale Semiconductor, Inc, mc68hc08ln56 Datasheet - Page 120

• Manufacturer Part Number: mc68hc08ln56
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Serial Peripheral Interface Module (SPI)
The transmit data buffer allows back-to-back transmissions without the slave precisely timing its writes
between transmissions as in a system with a single data buffer. Also, if no new data is written to the data
buffer, the last value contained in the shift register is the next data word to be transmitted.
For an idle master or idle slave that has no data loaded into its transmit buffer, the SPTE is set again no
more than two bus cycles after the transmit buffer empties into the shift register. This allows the user to
queue up a 16-bit value to send. For an already active slave, the load of the shift register cannot occur
until the transmission is completed. This implies that a back-to-back write to the transmit data register is
not possible. The SPTE indicates when the next write can occur.
120
SPSCK CYCLE
(CPHA = 1)
(CPHA = 0)
NUMBER
SPSCK
SPSCK
CLOCK
CLOCK
CLOCK
CLOCK
CLOCK
BUS
BUS
BUS
BUS
BUS
MOSI
MC68HC08LN56 • MC68HC708LN56 General Release Specification, Rev. 2.1
TO SPDR
TO SPDR
TO SPDR
TO SPDR
WRITE
WRITE
WRITE
WRITE
TO SPDR
WRITE
Figure 11-7. Transmission Start Delay (Master)
EARLIEST LATEST
EARLIEST
EARLIEST
EARLIEST
INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN
(SPSCK = INTERNAL CLOCK ÷ 128;
(SPSCK = INTERNAL CLOCK ÷ 32;
(SPSCK = INTERNAL CLOCK ÷ 2;
(SPSCK = INTERNAL CLOCK ÷ 8;
128 POSSIBLE START POINTS)
INITIATION DELAY
32 POSSIBLE START POINTS)
2 POSSIBLE START POINTS)
8 POSSIBLE START POINTS)
MSB
1
BIT 6
2
LATEST
LATEST
LATEST
BIT 5
3
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