mc68hc08ln56 Freescale Semiconductor, Inc, mc68hc08ln56 Datasheet - Page 56

• Manufacturer Part Number: mc68hc08ln56
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Clock Generator Module (CGMB)
Obviously, the acquisition and lock times can vary according to how large the frequency error is and may
be shorter or longer in many cases.
4.8.2 Parametric Influences on Reaction Time
Acquisition and lock times are designed to be as short as possible while still providing the highest possible
stability. These reaction times are not constant, however. Many factors directly and indirectly affect the
acquisition time.
The most critical parameter which affects the reaction times of the PLL is the reference frequency, f
This frequency is the input to the phase detector and controls how often the PLL makes corrections. For
stability, the corrections must be small compared to the desired frequency, so several corrections are
required to reduce the frequency error. Therefore, the slower the reference the longer it takes to make
these corrections. This parameter is under user control via the choice of crystal frequency f
value programmed in the reference divider. (See
4.5.6 PLL Reference Divider Select
Another critical parameter is the external filter capacitor. The PLL modifies the voltage on the VCO by
adding or subtracting charge from this capacitor. Therefore, the rate at which the voltage changes for a
given frequency error (thus change in charge) is proportional to the capacitor size. The size of the
capacitor also is related to the stability of the PLL. If the capacitor is too small, the PLL cannot make small
enough adjustments to the voltage and the system cannot lock. If the capacitor is too large, the PLL may
not be able to adjust the voltage in a reasonable time. (See
Also important is the operating voltage potential applied to V
characteristics of the PLL. A fixed value is best. Variable supplies, such as batteries, are acceptable if
they vary within a known range at very slow speeds. Noise on the power supply is not acceptable,
because it causes small frequency errors which continually change the acquisition time of the PLL.
Temperature and processing also can affect acquisition time because the electrical characteristics of the
PLL change. The part operates as specified as long as these influences stay within the specified limits.
External factors, however, can cause drastic changes in the operation of the PLL. These factors include
noise injected into the PLL through the filter capacitor, filter capacitor leakage, stray impedances on the
circuit board, and even humidity or circuit board contamination.
4.8.3 Choosing a Filter Capacitor
As described in
to the stability and reaction time of the PLL. The PLL is also dependent on reference frequency and supply
voltage. The value of the capacitor must, therefore, be chosen with supply potential and reference
56
•
(f
Manual and Automatic PLL Bandwidth
becomes set in the PLL bandwidth control register (PBWC).
Lock time, t
and the desired output frequency to less than the lock mode entry tolerance, ∆
based on an initial frequency error, (f
bandwidth control mode, lock time expires when the LOCK bit becomes set in the PLL bandwidth
control register (PBWC). (See
DES
– f
ORIG
4.8.2 Parametric Influences on Reaction
)/f
LOCK
MC68HC08LN56 • MC68HC708LN56 General Release Specification, Rev. 2.1
DES
, is the time the PLL takes to reduce the error between the actual output frequency
, of not more than ±100 percent. In automatic bandwidth control mode (See
Register.)
4.3.5 Manual and Automatic PLL Bandwidth
DES
Modes.), acquisition time expires when the ACQ bit
– f
4.3.3 PLL
ORIG
)/f
DES
Time, the external filter capacitor, C
, of not more than ±100 percent. In automatic
Circuits,
4.8.3 Choosing a Filter
DDA
. The power supply potential alters the
4.3.6 Programming the
Modes.)
Freescale Semiconductor
Capacitor.)
LOCK
. Lock time is
XCLK
PLL, and
F
, is critical
and the R
4.3.5
RDV
.