mc68hc08ln56 Freescale Semiconductor, Inc, mc68hc08ln56 Datasheet - Page 184

• Manufacturer Part Number: mc68hc08ln56
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Analog-to-Digital Converter (ADC)
14.7.2 ADC Data Register
One 8-bit result register is provided. This register is updated each time an ADC conversion completes.
14.7.3 ADC Clock Register
This register selects the clock frequency for the ADC.
ADIV2:ADIV0 — ADC Clock Prescaler Bits
ADICLK — ADC Input Clock Select
184
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate
the internal ADC clock.
set to approximately 1 MHz.
ADICLK selects either bus clock or CGMXCLK as the input clock source to generate the internal ADC
clock. Reset selects CGMXCLK as the ADC clock source.
If the external clock (CGMXCLK) is equal to or greater than 1 MHz, CGMXCLK can be used as the
clock source for the ADC. If CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as the
clock source. As long as the internal ADC clock is at approximately 1 MHz, correct operation can be
guaranteed.
1 = Internal bus clock
0 = External clock (CGMXCLK)
ADCLKR
Reset:
$0041
Read:
Write:
ADR
Reset:
$0042
Read:
Write:
MC68HC08LN56 • MC68HC708LN56 General Release Specification, Rev. 2.1
Bit 7
AD7
ADIV2
0
Bit 7
0
Table 14-2
ADIV2
Figure 14-4. ADC Clock Register (ADCLKR)
X = don’t care
= Unimplemented
0
0
0
0
1
= Unimplemented
Figure 14-3. ADC Data Register (ADR)
AD6
ADIV1
6
0
Table 14-2. ADC Clock Divide Ratio
1 MHz
6
0
shows the available clock configurations. The ADC clock should be
ADIV1
0
0
1
1
X
AD5
=
ADIV0
5
0
5
0
ADC input clock frequency
-----------------------------------------------------------------------
ADIV0
AD4
ADICLK
X
0
1
0
1
4
0
ADIV 2:0
4
0
[
ADC input clock / 16
AD3
ADC input clock / 2
ADC input clock / 4
ADC input clock / 8
ADC input clock /1
ADC Clock Rate
3
0
0
3
0
]
AD2
2
0
2
0
0
AD1
1
0
1
0
0
Freescale Semiconductor
Bit 0
AD0
0
Bit 0
0
0