mc68hc08ln56 Freescale Semiconductor, Inc, mc68hc08ln56 Datasheet - Page 212

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mc68hc08ln56

Manufacturer Part Number
mc68hc08ln56
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Break Module (BREAK)
17.3.1 Flag Protection During Break Interrupts
The system integration module (SIM) controls whether or not module status bits can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. (See
Break Interrupts subsection for each module.)
17.3.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
17.3.3 TIM During Break Interrupts
A break interrupt stops the timer counter.
212
Loading the instruction register with the SWI instruction
Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD in monitor mode)
Break Status/Control Register
Break Address Register High
Break Address Register Low
Register Name
MC68HC08LN56 • MC68HC708LN56 General Release Specification, Rev. 2.1
(BRKSCR)
IAB[15:0]
(BRKH)
(BRKL)
Figure 17-1. Break Module Block Diagram
BRKE
Figure 17-2. Break I/O Register Summary
Bit 15
Bit 7
Bit 7
IAB[15:8]
IAB[7:0]
= Unimplemented
BREAK ADDRESS REGISTER HIGH
BREAK ADDRESS REGISTER LOW
BRKA
14
6
6
5.7.3 SIM Break Flag Control Register (SBFCR)
8-BIT COMPARATOR
8-BIT COMPARATOR
13
5
5
12
4
4
11
3
3
CONTROL
10
2
2
1
9
1
BKPT
(TO SIM)
Freescale Semiconductor
Bit 0
Bit 8
Bit 0
and see the
$FE0C
$FE0D
$FE0E
Addr.

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