mc68hc08ln56 Freescale Semiconductor, Inc, mc68hc08ln56 Datasheet - Page 48

• Manufacturer Part Number: mc68hc08ln56
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Clock Generator Module (CGMB)
4.4.5 PLL Analog Ground Pin (V
V
potential as the V
4.4.6 Buffered Crystal Clock Output (CGMVOUT)
CGMVOUT buffers the OSC1 clock for external use.
4.4.7 CGMVSEL
CGMVSEL must be tied low or floated.
4.4.8 Oscillator Enable Signal (SIMOSCEN)
The SIMOSCEN signal comes from the system integration module (SIM) and enables the oscillator and
PLL.
4.4.9 Crystal Output Frequency Signal (CGMXCLK)
CGMXCLK is the crystal oscillator output signal. It runs at the full speed of the crystal (f
directly from the crystal oscillator circuit.
and OSC2 and may not represent the actual circuitry. The duty cycle of CGMXCLK is unknown and may
depend on the crystal and other external factors. Also, the frequency and amplitude of CGMXCLK can be
unstable at startup.
4.4.10 CGMB Base Clock Output (CGMOUT)
CGMOUT is the clock output of the CGMB. This signal goes to the SIM, which generates the MCU clocks.
CGMOUT is a 50 percent duty cycle clock running at twice the bus frequency. CGMOUT is software
programmable to be either the oscillator output, CGMXCLK, divided by two or the VCO clock, CGMVCLK,
divided by two.
4.4.11 CGMB CPU Interrupt (CGMINT)
CGMINT is the interrupt signal generated by the PLL lock detector.
4.5 CGMB Registers
These registers control and monitor operation of the CGMB:
48
SSA
•
•
•
•
•
•
is a ground pin used by the analog portions of the PLL. Connect the V
PLL control register (PCTL) (See
PLL bandwidth control register (PBWC) (See
PLL multiplier select register high (PMSH) (See
PLL multiplier select register low (PMSL) (See
PLL VCO range select register (PVRS) (See
PLL reference divider select register (PRDS) (See
Route V
capacitors as close as possible to the package.
SS
MC68HC08LN56 • MC68HC708LN56 General Release Specification, Rev. 2.1
pin.
SSA
carefully for maximum noise immunity and place bypass
SSA
Figure 4-2
4.5.1 PLL Control
)
NOTE
shows only the logical relation of CGMXCLK to OSC1
4.5.5 PLL VCO Range Select
4.5.2 PLL Bandwidth Control
4.5.4 PLL Multiplier Select Register
4.5.3 PLL Multiplier Select Register
4.5.6 PLL Reference Divider Select
Register.)
SSA
pin to the same voltage
Register.)
Register.)
Freescale Semiconductor
XCLK
Low.)
High.)
) and comes
Register.)