l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet - Page 10

• Manufacturer Part Number: l-fw32206t100
• Description: 1394a Phy/link Open Host Controller
• Manufacturer: ETC-unknow

FW322 06 T100
1394a PCI PHY/Link Open Host Controller
FW322 Functional Description
Asynchronous Transmit DMA (ASYNC_TX DMA,
ASYNC_TX_ADMIN)
The ASYNC_TX DMA and ASYNC_TX_ADMIN blocks
of the FW322 manage the asynchronous transmission
of either request or response packets. The mechanism
for asynchronous transmission of requests and
responses is similar. The only difference is the system
memory location of the buffer descriptor list when
processing the two contexts. Therefore, the discussion
below, which pertains to asynchronous transmit
requests, parallels that of asynchronous transmit
responses.
The FW322 asynchronous transmission of packets
involves the following steps:
1. Fetch complete buffer descriptor block from host
2. Get data from system memory and store into
3. Request transfer of data from FIFO to the link core.
4. Handle retries, if any.
5. Handle errors in steps 1 to 4.
6. End the transfer if there are no errors.
Asynchronous Receive DMA (ASYNC_RX DMA,
ASYNC_RX_ADMIN)
The ASYNC_RX DMA and ASYNC_RX_ADMIN blocks
of the FW322 manage the processing of received
packets. Data packets are parsed and stored in a
dedicated asynchronous receive (AR) FIFO. Command
descriptors are read through the PCI interface to
determine the disposition of the data arriving through
the 1394 link.
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memory.
asynchronous transmit (AT) FIFO.
(continued)
The header of the received packet is processed to
determine, among other things, the following:
1. The type of packet received.
2. The source and destinations.
3. The data and size, if any.
4. Any required operation, for example, compare and
The asynchronous data transfer block also handles
DMA transfers of SelfID packets during the 1394 bus
initialization phase and block transactions associated
with physical requests.
Physical Request/Response DMA
The Physical DMA block within the FW322 is responsi-
ble for processing incoming physical requests and out-
going physical responses. When an incoming
asynchronous packet is received, the FW322 will pro-
cess the packet automatically without software inter-
vention if the packet meets a set of criteria defined
within the OHCI specification. When the criteria are
met, the asynchronous packet is reclassified as a phys-
ical packet. Requests that do not meet the criteria
remain asynchronous packets and are processed as
described above in the Asynchronous Receive DMA
section. Processing packets as physical requests/
responses allows the FW322 to either receive or trans-
mit an asynchronous packet without the use of DMA
descriptors. Instead, the FW322 directly writes or reads
data to/from memory using the address defined within
the packet header. Since physical packets can be pro-
cessed independently of the system’s software and
CPU, processing a packet as physical results in a sys-
tem performance optimization.
SelfID DMA
The SelfID DMA block within the FW322 is responsible
for receiving SelfID packets during the bus initialization
process. The received SelfID packets are written into a
software-defined host memory buffer.
swap operation.
Data Sheet, Rev. 1
December 2005
Agere Systems Inc.