l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet - Page 63

• Manufacturer Part Number: l-fw32206t100
• Description: 1394a Phy/link Open Host Controller
• Manufacturer: ETC-unknow

Data Sheet, Rev. 1
December 2005
Internal Registers
Isochronous Transmit Context Control (IT DMA ContextControl) Register
The Isochronous Transmit Context Control set/clear register controls options, state, and status for the
isochronous transmit DMA contexts. The n value in the following register addresses indicates the context number
(n = 0:7).
Offset:
Default:
Reference:
Table 55. Isochronous Transmit Context Control Register Description
Agere Systems Inc.
30:16
14:13
9:5
4:0
Bit
31
15
12
10
11
cycleMatchEnable
Field Name
cycleMatch
event code
204h + (16 * n) clear register
XXXX X0XXh
1394 Open Host Controller Specification, Rev. 1.1, Sections 9.2, 3.1.1
Reserved
Reserved
200h + (16 * n) set register
active
wake
dead
run
(continued)
RSCU
RSCU
Type
RSC
RSU
RU
RU
RU
R
R
When this bit is set to 1, processing occurs such that the packet
described by the context’s first descriptor block is transmitted in the
cycle whose number is specified in the cycleMatch field (bits 30:16).
The cycleMatch field (bits 30:16) must match the low-order 2 bits of
cycleSeconds and the 13-bit cycleCount field in the cycle start packet
that is sent or received immediately before isochronous transmission
begins. Since the isochronous transmit DMA controller may work
ahead, the processing of the first descriptor block may begin slightly in
advance of the actual cycle in which the first packet is transmitted. The
effects of this bit, however, are impacted by the values of other bits in
this register and are explained in the 1394 Open Host Controller Inter-
face Specification. Once the context has become active, hardware
clears this bit.
Contains a 15-bit value, corresponding to the low-order 2 bits of the
bus isochronous Cycle Time register cycleSeconds field (bits 31: 25)
and the cycleCount field (bits 24:12) (see Table 48). If bit 31
(cycleMatchEnable) is set, then this isochronous transmit DMA context
becomes enabled for transmits when the low-order 2 bits of the bus
Isochronous Cycle Timer register cycleSeconds field (bits 31:25) and
the cycleCount field (bits 24:12) value equal this field’s (cycleMatch)
value.
This bit is set by software to enable descriptor processing for the
context and cleared by software to stop descriptor processing. The
FW322 changes this bit only on a hardware or software reset.
Reserved. Bits 14:13 return 0s when read.
Software sets this bit to cause the FW322 to continue or resume
descriptor processing. The FW322 clears this bit on every descriptor
fetch.
The FW322 sets this bit when it encounters a fatal error and clears the
bit when software resets bit 15 (run).
The FW322 sets this bit to 1 when it is processing descriptors.
Reserved. Bits 9:5 return 0s when read.
Following an OUTPUT_LAST* command, the error code is indicated in
this field. Possible values are ack_complete, evt_descriptor_read,
evt_data_read, and evt_unknown.
1394a PCI PHY/Link Open Host Controller
Description
FW322 06 T100
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