l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet - Page 77

• Manufacturer Part Number: l-fw32206t100
• Description: 1394a Phy/link Open Host Controller
• Manufacturer: ETC-unknow

Data Sheet, Rev. 1
December 2005
Crystal Selection Considerations
The FW322 is designed to use an external 24.576 MHz parallel resonant fundamental mode crystal connected
between the XI and XO terminals to provide the reference for an internal oscillator circuit. The IEEE 1394 a-2000
standard requires that FW322 have less than ±100 ppm total variation from the nominal data rate, which is directly
influenced by the crystal. To achieve this, it is recommended that an oscillator with a nominal 50 ppm or less fre-
quency tolerance be used.
The total frequency variation must be kept below ±100 ppm from nominal with some allowance for error introduced
by board and device variations. Trade-offs between frequency tolerance and stability may be made as long as the
total frequency variation is less than ±100 ppm.
Load Capacitance
The frequency of oscillation is dependent upon the load capacitance specified for the crystal, in parallel resonant
mode crystal circuits. Total load capacitance (C
capacitances from the FW322 board traces and capacitances of the other FW322 connected components. The val-
ues for load capacitors (C
C
Where:
C
C
R
Adjustment to Crystal Loading
The resistor (R
approximately 400 Ω. A more precise value for this resistor is dependent on the specific crystal used. Please refer to
the crystal manufacturer’s data sheet and application notes to determine an appropriate value for R
value for this resistor can be obtained by placing different values of RL on a production board and using an oscillo-
scope to view the resultant clock waveform at node A for each resistor value. The desired waveform should have the
following characteristics: the waveform should be sinusoidal, with an amplitude as large as possible, but not greater
than 3.3 V or less than 0 V.
Crystal/Board Layout
The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency and minimizing
noise introduced into the FW322 PLL. The crystal and two load capacitors (C
during layout. They should be placed as close as possible to one another, while minimizing the loop area created by
the combination of the three components. Minimizing the loop area minimizes the effect of the resonant current that
flows in this resonant circuit. This layout unit (crystal and load capacitors) should then be placed as close as possible
to the PHY XI and XO terminals to minimize trace lengths. Vias should not be used to route the XI and XO signals.
Agere Systems Inc.
L
stray
L
A
= load capacitance specified by the crystal manufacturer.
= load resistance; nominal value is 400 Ω; the best value to be used can be determined by customer testing.
= C
= capacitance of the board and the FW322, typically 2 pF—3 pF.
B
= (C
L
– C
L
) in Figure 7 is recommended for fine-tuning the crystal circuit. The nominal value for this resistor is
stray
) × 2
A
and C
B
) should be calculated using this formula:
XI
XO
Figure 7. Crystal Circuitry
L
R
) is a function of not only the discrete load capacitors, but also
L
A
C
C
B
A
1394a PCI PHY/Link Open Host Controller
A
+ C
B
) should be considered as a unit
FW322 06 T100
L
. A more precise
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