l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet - Page 72

• Manufacturer Part Number: l-fw32206t100
• Description: 1394a Phy/link Open Host Controller
• Manufacturer: ETC-unknow

FW322 06 T100
1394a PCI PHY/Link Open Host Controller
Internal Register Configuration
PHY Core Register Fields
Table 65. PHY Core Register Fields
72
72
Physical_ID
Max_speed
Gap_count
Total_ports
Contender
Pwr_class
Extended
Delay
Field
RHB
LCtrl
Jitter
IBR
PS
R
(In Bits)
Size
6
1
1
1
1
6
3
4
3
4
1
1
3
3
Type Power Reset
RW
RW
RW
RW
RW
RW
R
R
R
R
R
R
R
R
description
description
000000
Value
010
0000
3F
See
See
000
—
0
0
0
7
2
1
16
2
(continued)
The address of this node is determined during self-identification. A
value of 63 indicates a misconfigured bus; therefore, the link will not
transmit any packets.
When set to one, indicates that this node is the root.
Cable Power Active. The PHY core sets this bit when cable power
measured at the connector is at least 7.5 V. The PHY core clears
this bit when the detectable voltage is below this value.
Root Hold-Off Bit. When set to one, the force_root variable is
TRUE. This instructs the PHY core to attempt to become the root
during the next tree identify process.
Initiate Bus Reset. When set to one, instructs the PHY core to set
ibr TRUE and reset_time to RESET_TIME. These values, in turn,
cause the PHY core to initiate a bus reset without arbitration; the
reset signal is asserted for 166 µs. This bit is self-clearing.
Used to configure the arbitration timer setting to optimize gap times
according to the topology of the bus. See Section 4.3.6 of IEEE
Standard 1394 a-2000 for the encoding of this field.
This field has a constant value of seven, which indicates the
extended PHY Core register map.
The number of ports implemented by this PHY core. This count
reflects the number.
Indicates the speed(s) this PHY core supports:
000
001
010
011
100
101
All other values are reserved for future definition.
Worst-case repeater delay; total worst-case repeater delay = [144 +
(delay * 20)] ns.
Link Active. Cleared or set by software to control the value of the L
bit transmitted in the node’s SelfID packet 0, which will be the logical
AND of this bit and LPS active.
Cleared or set by software to control the value of the C bit transmit-
ted in the SelfID packet. Powerup reset value is 0.
The difference between the fastest and slowest repeater data delay
= [(Jitter + 1) * 20] ns.
Power Class. Controls the value of the pwr field transmitted in the
SelfID packet. See Section 4.3.4.1 of IEEE Standard 1394 a-2000 for
the encoding of this field. The PC2 pin determines the least signifi-
cant bit of the power reset value. The two most significant bits
default to a power reset value of 00.
2
2
2
2
2
2
= 98.304, 196.608, 393.216, and 786.43 Mbits/s.
= 98.304 Mbits/s.
= 98.304 and 196.608 Mbits/s.
= 98.304, 196.608, and 393.216 Mbits/s.
= 98.304, 196.608, 393.216, 786.432, and
= 98.304, 196.608, 393.216, 786.432, 1,572.864, and
1,572.864 Mbits/s.
3,145.728 Mbits/s.
Description
Data Sheet, Rev. 1
December 2005
Agere Systems Inc.