l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet - Page 73

• Manufacturer Part Number: l-fw32206t100
• Description: 1394a Phy/link Open Host Controller
• Manufacturer: ETC-unknow

Data Sheet, Rev. 1
December 2005
Internal Register Configuration
Table 65. PHY Core Register Fields (continued)
Agere Systems Inc.
Page_select
Enab_accel
Enab_multi
Port_select
Port_event
Watchdog
Pwr_fail
Timeout
Field
ISBR
Loop
Size Type Power Reset Value
1
1
1
1
1
1
1
1
3
4
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0000
000
0
0
0
1
0
0
0
0
(continued)
When set to one, the PHY core will set Port_event to one if
resume operations commence for any port.
Initiate Short (Arbitrated) Bus Reset. A write of one to this bit
instructs the PHY core to set ISBR true and reset_time to
SHORT_RESET_TIME. These values, in turn, cause the PHY
core to arbitrate and issue a short bus reset. This bit is self-
clearing.
Loop Detect. A write of one to this bit clears it to zero.
Cable Power Failure Detect. Set to one when the PS bit
changes from one to zero. A write of one to this bit clears it to
zero.
Arbitration State Machine Time-Out. A write of one to this bit
clears it to zero (see MAX_ARB_STATE_TIME).
Port Event Detect. The PHY core sets this bit to one if any of
connected, bias, disabled, or fault change for a port whose
Int_enable bit is one. The PHY core also sets this bit to one if
resume operations commence for any port and watchdog bit is
one. A write of one to this bit clears it to zero.
Enable Arbitration Acceleration. When set to one, the PHY
core will use the enhancements specified in clause 4.4 of
1394a-2000 Specification. PHY core behavior is unspecified if
the value of Enab_accel is changed while a bus request is
pending.
Enable Multispeed Packet Concatenation. When set to one,
the link will signal the speed of all packets to the PHY core.
Selects which of eight possible PHY Core register pages are
accessible through the window at PHY Core register addresses
1000
If the page selected by Page_select presents per-port informa-
tion, this field selects which port’s registers are accessible
through the window at PHY Core register addresses 1000
through 1111
starting at zero, p0.
2
through 1111
1394a PCI PHY/Link Open Host Controller
2
, inclusive. Ports are numbered monotonically
2
, inclusive.
Description
FW322 06 T100
2
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