l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet - Page 23

• Manufacturer Part Number: l-fw32206t100
• Description: 1394a Phy/link Open Host Controller
• Manufacturer: ETC-unknow

Data Sheet, Rev. 1
December 2005
Internal Registers
PCI Command Register
The Command register provides control over the FW322 interface to the PCI bus. All bit functions adhere to the
definitions in the PCI Local Bus Specification, as in the following bit descriptions.
Offset:
Default:
Type:
Reference:
Table 4. PCI Command Register Description
Agere Systems Inc.
15:10
Bit
9
8
7
6
5
4
3
2
1
0
MEMORY_ENB
MASTER_ENB
SERR_ENB
PERR_ENB
Field Name
STEP_ENB
VGA_ENB
MWI_ENB
FBB_ENB
0000h
PCI Local Bus Specification, Rev. 2.2, Section 6.2.2 and 1394 Open Host Controller Interface
Specification, Rev. 1.1, Section A.3.1
04h
Read/write
Reserved
SPECIAL
IO_ENB
(continued)
Type
RW
RW
RW
RW
RW
R
R
R
R
R
R
Reserved. Bits 15:10 return 0s when read.
Fast Back-to-Back Enable. The FW322 does not generate fast back-
to-back transactions; thus, this bit returns 0 when read.
SERR Enable. When this bit is set, the FW322 SERR driver is enabled.
PCI_SERRN can be asserted after detecting an address parity error on
the PCI bus.
Address/Data Stepping Control. The FW322 does not support
address/data stepping; thus, this bit is hardwired to 0.
Parity Error Enable. When this bit is set, the FW322 is enabled to drive
PERR response to parity errors through the PCI_PERRN signal.
VGA Palette Snoop Enable. The FW322 does not feature VGA palette
snooping. This bit returns 0 when read.
Memory Write and Invalidate Enable. When this bit is set, the FW322
is enabled to generate MWI PCI bus commands. If this bit is reset, then
the FW322 generates memory write commands instead.
Special Cycle Enable. The FW322 function does not respond to special
cycle transactions. This bit returns 0 when read.
Bus Master Enable. When this bit is set, the FW322 is enabled to
initiate cycles on the PCI bus.
Memory Response Enable. Setting this bit enables the FW322 to
respond to memory cycles on the PCI bus. This bit must be set to access
OHCI registers.
I/O Space Enable. The FW322 does not implement any I/O mapped
functionality; thus, this bit returns 0 when read.
1394a PCI PHY/Link Open Host Controller
Description
FW322 06 T100
23