l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet - Page 65

• Manufacturer Part Number: l-fw32206t100
• Description: 1394a Phy/link Open Host Controller
• Manufacturer: ETC-unknow

Data Sheet, Rev. 1
December 2005
Internal Registers
Isochronous Receive Context Control (IR DMA ContextControl) Register
The Isochronous Receive Context Control set/clear register controls options, state, and status for the isochronous
receive DMA contexts. The n value in the following register addresses indicates the context number (n = 0:7).
Offset:
Default:
Reference:
Table 57. Isochronous Receive Context Control Register Description
Agere Systems Inc.
26:16
Bit
31
30
29
28
27
cycleMatchEnable
dualBufferMode
multiChanMode
isochHeader
Field Name
Reserved
404h + (32 *n) clear register
X000 X0XXh
1394 Open Host Controller Specification, Rev. 1.1, Sections 10.3, 3.1.2
400h + (32 * n) set register
bufferFill
(continued)
RSCU When this bit is set, the context begins running only when the 15-bit
Type
RSC
RSC
RSC
RSC
R
When this bit is set, received packets are placed back-to-back to com-
pletely fill each receive buffer. When this bit is cleared, each received
packet is placed in a single buffer. If bit 28 (multiChanMode) is set to 1,
then this bit must also be set to 1. The value of this bit must not be
changed while bit 10 (active) or bit 15 (run) is set.
When this bit is 1, received isochronous packets include the complete
4-byte isochronous packet header seen by the link layer. The end of the
packet is marked with an xferStatus in the first doublet, and a 16-bit
timeStamp indicating the time of the most recently received (or sent)
cycleStart packet. When this bit is cleared, the packet header is stripped
off of received isochronous packets. The packet header, if received,
immediately precedes the packet payload. The value of this bit must not
be changed while bit 10 (active) or bit 15 (run) is set.
cycleMatch field (bits 26:12) in the IRContext Match register (see Table
59) matches the two low-order bits of the CycleSeconds field and the
13-bit CycleCount field in the CycleTimer register. The effects of this bit,
however, are impacted by the values of other bits in this register. Once
the context has become active, hardware clears this bit. The value of this
bit must not be changed while bit 10 (active) or bit 15 (run) is set.
When this bit is set, the corresponding isochronous receive DMA context
receives packets for all isochronous channels enabled in the Isochro-
nous Receive Channel Mask High and Isochronous Receive Channel
mask Low registers. The isochronous channel number specified in the
isochronous receive DMA Context Match register is ignored. When this
bit is cleared, the isochronous receive DMA context receives packets for
the channel number specified in the Context Match register. Only one
isochronous receive DMA context may use the Isochronous Receive
Channel Mask registers. If more than one Isochronous Receive Context
Control register has this bit set, then results are undefined. The value of
this bit must not be changed while bit 10 (active) or bit 15 (run) is set to 1.
When this bit is set, received packets are separated into first and second
payload and streamed independently to the first buffer series and second
buffer series (see OHCI v.1.1, 10.2.3). Both multiChanMode and buffer
fill must be programmed to zero when this bit is set. The value of
dualBufferMode will not be changed while active or run is set.
Reserved. Bits 26:16 return 0s when read.
1394a PCI PHY/Link Open Host Controller
Description
FW322 06 T100
65