l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet - Page 14

• Manufacturer Part Number: l-fw32206t100
• Description: 1394a Phy/link Open Host Controller
• Manufacturer: ETC-unknow

FW322 06 T100
1394a PCI PHY/Link Open Host Controller
FW322 Functional Description
An external resistor sets the driver output current,
along with other internal operating currents. This
resistor is connected between the R0 and R1 signals
and has a value of 2.49 kΩ ± 1%.
The C bit (20) in the SelfID packet (see Section 4.3.4.1
of the IEEE 1394a-2000 specification for more details)
has a default value of 0 which means this node is not a
contender for bus manager. A value of 0 still allows this
node to be considered by software for bus manager.
The least significant bit (23) in the Power Class (Pwr)
field in the SelfID packet is set to the value of the PC2
pin. The two most significant bits (21 and 22) in the
Pwr field are set to a default of 00. The PC2 pin is tied
low or high to create a Pwr field of 000 (PC2 low) or
001 (PC2 high). See Section 4.3.4.1 of the IEEE
1394a-2000 specification for additional details.
When the power supply of the PHY core is removed
while the twisted-pair cables are connected, the PHY
core transmitter and receiver circuitry has been
designed to present a high impedance to the cable in
order to not load the TPBIAS signal voltage on the
other end of the cable.
Whenever the TPA±/TPB± signals are wired to a
connector, they must be terminated using the normal
termination network. This is required for reliable
operation. For those applications when one or more of
the FW322 ports are not wired to a connector, those
unused ports may be left unconnected without normal
termination. When a port does not have a cable
connected, internal connect-detect circuitry will keep
the port in a disconnected state.
14
(continued)
Note: All gap counts on all nodes of a 1394 bus must
The internal link power status (LPS) signal works with
the internal LKON signal to manage the LLC power
usage of the node. The LPS signal indicates if the LLC
of the node is powered up or down. If LPS is inactive
for more than 1.2 µs and less than 25 µs, the internal
PHY/link interface is reset.
If LPS is inactive for greater than 25 µs, the PHY will
disable the internal PHY/link interface to save power.
The FW322 continues its repeater function even when
the PHY/link interface is disabled. If the PHY then
receives a link-on packet, the internal LKON signal is
activated to output a 6.114 MHz signal, which can be
used by the LLC to power itself up. Once the LLC is
powered up, the internal LPS signal communicates this
to the PHY and the internal PHY/link interface is
enabled. The internal LKON signal is turned off when
the LCtrl bit is set. (For more information on this bit,
refer to the Table 65 on PHY Core Register Fields in
this data sheet.)
Six of the FW322 pins are used to set up various test
conditions used only during the device manufacturing
process. These pins are SE, SM, TEST0, TEST1,
TEST2, and PTEST.
be identical. The software accomplishes this by
issuing PHY core configuration packets (see
Section 4.3.4.3 of IEEE 1394-1995 and 1394a-
2000 standards) or by issuing two bus resets,
which resets the gap counts to the maximum
level (3Fh).
Data Sheet, Rev. 1
December 2005
Agere Systems Inc.