l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet - Page 59

• Manufacturer Part Number: l-fw32206t100
• Description: 1394a Phy/link Open Host Controller
• Manufacturer: ETC-unknow

Data Sheet, Rev. 1
December 2005
Internal Registers
Asynchronous Request Filter High Register
The Asynchronous Request Filter High set/clear register is used to enable asynchronous receive requests on a
per-node basis, and handles the upper node IDs. When a packet is destined for either the physical request context
or the ARRQ context, the source node ID is examined. If the bit corresponding to the node ID is not set in this reg-
ister, then the packet is not acknowledged and the request is not queued. The node ID comparison is done if the
source node is on the same bus as the FW322. All nonlocal bus-sourced packets are not acknowledged unless
bit 31 in this register is set.
Offset:
Default:
Reference:
Table 49. Asynchronous Request Filter High Register Description
Asynchronous Request Filter Low Register
The Asynchronous Request Filter Low set/clear register is used to enable asynchronous receive requests on a
per-node basis, and handles the lower node IDs. Other than filtering different node IDs, this register behaves
identically to the Asynchronous Request Filter High register.
Offset:
Default:
Reference:
Table 50. Asynchronous Request Filter Low Register Description
Agere Systems Inc.
30:0 asynReqResourceN RSCU If this bit is set, then asynchronous requests received from node N (where
31:0 asynReqResourceN RSCU If this bit is set for local bus node number N (where N = the bit number from
Bit
Bit
31
asynReqResourceAll RSCU If this bit is set, then all asynchronous requests received by the FW322 from
Field Name
Field Name
104h clear register
0000 0000h
1394 Open Host Controller Specification, Rev. 1.1, Section 5.14
10Ch clear register
0000 0000h
1394 Open Host Controller Specification, Rev. 1.1, Section 5.14
100h set register
108h set register
(continued)
Type
Type
nonlocal bus nodes are accepted and the values of all asynReqResourceN
bits will be ignored. Set/Clear operations to this register while the
IntEvent.busReset bit (see Table 39) is asserted will have no effect. A bus
reset will not affect the value of the asynReqResourceAll bit.
N = the bit number + 32) on local bus are accepted by FW322. All asyn-
ReqResourceN bits will be cleared to zero when a bus reset occurs. Set/
Clear operations to this register while the IntEvent.busReset bit (see Table
39) is asserted will have no effect.
0 to 31), then asynchronous requests received by the FW322 from that node
are accepted. All asynReqResourceN bits will be cleared to zero when a bus
reset occurs. Set/Clear operations to this register while the
IntEvent.busReset bit (see Table 39) is asserted will have no effect.
1394a PCI PHY/Link Open Host Controller
Description
Description
FW322 06 T100
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