l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet - Page 28

• Manufacturer Part Number: l-fw32206t100
• Description: 1394a Phy/link Open Host Controller
• Manufacturer: ETC-unknow

FW322 06 T100
1394a PCI PHY/Link Open Host Controller
Internal Registers
Interrupt Line and Pin Register
The Interrupt Line and Pin register is used to communicate interrupt line routing information.
Offset:
Default:
Type:
Reference:
Table 11. Interrupt Line and Pin Register Description
MIN_GNT and MAX_LAT Register
The MIN_GNT and MAX_LAT register is used to communicate to the system the desired setting of the Latency
Timer register. If a serial EEPROM is detected, then the contents of this register are loaded from the serial
EEPROM interface after a PCI reset. If no serial EEPROM is detected, then this register returns a default value
that corresponds to the MIN_GNT = 0Ch, MAX_LAT = 18h.
Offset:
Default:
Type:
Reference:
Table 12. MIN_GNT and MAX_LAT Register Description
28
28
15:8
15:8
Bit
7:0
Bit
7:0
PCI Local Bus Specification, Rev. 2.2, Section 6.2.4 and 6.7
Field Name
Field Name
3Ch
0100h
Read only
3Eh
180Ch
Read only
PCI Local Bus Specification, Rev. 2.2, Section 6.2.4
INTR_LINE
INTR_PIN
MAX_LAT
MIN_GNT
(continued)
Type
Type
RW
RU
RU
R
Interrupt Pin Register. This register returns 01h when read, indi-
cating that the FW322 PCI function signals interrupts on the INTA pin.
Interrupt Line Register. This register is programmed by the system
and indicates to software to which interrupt line the FW322 INTA is
connected.
Maximum Latency. The contents of this register may be used by host
BIOS to assign an arbitration priority level to the FW322. The default
for this register (18h) indicates that the FW322 may need to access
the PCI bus as often as every 0.25 µs; thus, an extremely high-priority
level is requested. The contents of this field may also be loaded from
the serial ROM.
Minimum Grant. The contents of this register may be used by host
BIOS to assign a Latency Timer register value to the FW322. The
default (0Ch) for this register indicates that the FW322 may need to
sustain burst transfers for nearly 64 µs; thus, requesting a large value
be programmed in the FW322 Latency Timer register. The contents of
this field may also be loaded from the serial ROM.
Description
Description
Data Sheet, Rev. 1
December 2005
Agere Systems Inc.