l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet - Page 24

• Manufacturer Part Number: l-fw32206t100
• Description: 1394a Phy/link Open Host Controller
• Manufacturer: ETC-unknow

FW322 06 T100
1394a PCI PHY/Link Open Host Controller
Internal Registers
PCI Status Register
The Status register provides status information for PCI bus related events. All bit functions adhere to the
definitions in the PCI Local Bus Specification, v.2.2, Table 6.2.
Offset:
Default:
Type:
Reference:
Table 5. PCI Status Register
24
24
10:9
Bit
3:0
15
14
13
12
11
8
7
6
5
4
TABORT_REC
TABORT_SIG
PCI_SPEED
PAR_ERR
SYS_ERR
FBB_CAP
DATAPAR
Reserved
Reserved
MABORT
CAPLIST
66MHZ
Name
Field
06h
0290h
Read/write
PCI Local Bus Specification, Rev. 2.2, Section 6.2.3 and 1394 Open Host Controller Interface
Specification, Rev. 1.1, Section A.3.2
(continued)
Type
RCU
RCU
RCU
RCU
RCU
RCU
R
R
R
R
R
R
Detected Parity Error. This bit must be set by the device whenever it
detects a parity error, even if parity error handling is disabled.
Signaled System Error. This bit must be set whenever the device
asserts SERR#.
Received Master Abort. This bit must be set by a master device
whenever its transaction (except for special cycle) is terminated with
master-abort.
Received Target Abort. This bit must be set by a master device
whenever its transaction is terminated with target-abort.
Signaled Target Abort. This bit must be set by a target device
whenever it terminates a transaction with target-abort.
DEVSEL Timing. Bits 9 and 10 encode the timing of DELSEL# (see
Section 3.6.1 of the PCI Specification). These bits must indicate the
slowest time that a device asserts DEVSEL# for any bus command
except configuration read and configuration write. The default timing is
01 (medium).
Master Data Parity Error. See Table 6-2 of the PCI Specification for
more information.
Fast Back-to-Back Capable. Indicates whether or not the target is
capable of accepting fast back-to-back transactions when the
transactions are not to the same agent. The FW322 does not support
back-to-back transactions.
Reserved.
66 MHz Capable. Indicates whether or not this device is capable of
running at 66 MHz as defined in Chapter 7 of the PCI Specification. The
FW322 reports a value of zero in this field indicating that 66 MHz
functionality is not supported.
Capabilities List. Indicates whether or not this device implements the
pointer for a New Capabilities linked list at offset 34h. A value of zero
indicates that no New Capabilities linked list is available. A value of one
indicates that the value read at offset 34h is a point in Configuration
Space to a linked list of new capabilities. (See Section 6.7 of the PCI
Specification for more details.)
Reserved.
Description
Data Sheet, Rev. 1
December 2005
Agere Systems Inc.