l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet - Page 53

• Manufacturer Part Number: l-fw32206t100
• Description: 1394a Phy/link Open Host Controller
• Manufacturer: ETC-unknow

Data Sheet, Rev. 1
December 2005
Internal Registers
Isochronous Transmit Interrupt Mask (isoXmitIntMask) Register
The Isochronous Transmit Interrupt Mask set/clear register is used to enable the isochTx interrupt source on a
per-channel basis. Reads from either the set register or the clear register, always return the contents of the
Isochronous Transmit Interrupt Mask register. In all cases, the enables for each interrupt event align with the
event register bits detailed in Table 42.
Offset:
Default:
Reference:
Table 42. Isochronous Transmit Interrupt Event Description
Agere Systems Inc.
31:8
7:0
Bit
isoXmit7:isoXmit0
9Ch clear register (returns IsoXmitEvent and IsoXmitMask when read)
0000 00XXh
1394 Open Host Controller Specification, Rev. 1.1, Section 6.3
98h set register
Field Name
Reserved
(continued)
RSCU
Type
R
Reserved. Bits 31:8 return 0s when read.
Setting one of these bits enables the corresponding interrupt
event in the isoXmitIntEvent register. Clearing a bit in this register
disables the corresponding interrupt event in the isoXmitIntEvent
register.
1394a PCI PHY/Link Open Host Controller
Description
FW322 06 T100
53