l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet - Page 54

• Manufacturer Part Number: l-fw32206t100
• Description: 1394a Phy/link Open Host Controller
• Manufacturer: ETC-unknow

FW322 06 T100
1394a PCI PHY/Link Open Host Controller
Internal Registers
Isochronous Receive Interrupt Event (isoRecvIntEvent) Register
The Isochronous Receive Interrupt Event set/clear register reflects the interrupt state of the isochronous receive
contexts. An interrupt is generated on behalf of an isochronous receive context if an INPUT_* command completes
and its interrupt bits are set. Upon determining that the interrupt event register isochRx (bit 7) interrupt has
occurred, software can check this register to determine which context(s) caused the interrupt. The interrupt bits are
set by an asserting edge of the corresponding interrupt signal, or by writing a 1 in the corresponding bit in the set
register. The only mechanism to clear the bits in this register is to write a 1 to the corresponding bit in the clear reg-
ister.
The isoRecvIntMask register is ANDed with the isoRecvIntEvent register to enable selected bits to generate pro-
cessor interrupts. Reading the isoRecvIntEventSet register returns the current state of the isoRecvIntEvent regis-
ter. Reading isoRecvIntEventClear register returns the masked version of the isoRecvIntEvent register, i.e., the bit-
wise AND function of isoRecvtIntEvent and isoRecvtIntMask.
Offset:
Default:
Reference:
Table 43. Isochronous Receive Interrupt Event Description
54
31:8
Bit
7
6
5
4
3
2
1
0
A0h set register
A4h clear register
0000 0000h
1394 Open Host Controller Specification, Rev. 1.1, Section 6.4
Field Name
Reserved
isoRecv7
isoRecv6
isoRecv5
isoRecv4
isoRecv3
isoRecv2
isoRecv1
isoRecv0
(continued)
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
Type
R
Reserved. Bits 31:8 return 0s when read.
Isochronous receive context 7 caused the interrupt event register bit
7 (isochRx) interrupt.
Isochronous receive context 6 caused the interrupt event register bit
7 (isochRx) interrupt.
Isochronous receive context 5 caused the interrupt event register bit
7 (isochRx) interrupt.
Isochronous receive context 4 caused the interrupt event register bit
7 (isochRx) interrupt.
Isochronous receive context 3 caused the interrupt event register bit
7 (isochRx) interrupt.
Isochronous receive context 2 caused the interrupt event register bit
7 (isochRx) interrupt.
Isochronous receive context 1 caused the interrupt event register bit
7 (isochRx) interrupt.
Isochronous receive context 0 caused the interrupt event register bit
7 (isochRx) interrupt.
Description
Data Sheet, Rev. 1
December 2005
Agere Systems Inc.