l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet - Page 55

• Manufacturer Part Number: l-fw32206t100
• Description: 1394a Phy/link Open Host Controller
• Manufacturer: ETC-unknow

Data Sheet, Rev. 1
December 2005
Internal Registers
Isochronous Receive Interrupt Mask (isoRecvIntMask) Register
The Isochronous Receive Interrupt Mask set/clear register is used to enable the isochRx interrupt source on a
per-channel basis. Reads from either the set register or the clear register always return the contents of the
Isochronous Transmit Interrupt Mask register. In all cases, the enables for each interrupt event correspond to the
isoRecvIntEvent register bits. Setting a bit in this register enables the corresponding interrupt event in the
isoRecvIntEvent register. Clearing a bit in this register disables the corresponding interrupt event in the
isoRecvIntEvent register.
Offset:
Default:
Reference:
Fairness Control Register
The Fairness Control register provides a mechanism by which software can direct the host controller to transmit
multiple asynchronous requests during a fairness interval, as specified by the IEEE-1394a Specification.
Offset:
Default:
Reference:
Table 44. Fairness Control Register Description
Agere Systems Inc.
31:8
7:0
Bit
Field Name Type
Reserved
pri_req
ACh clear register
0000 000Xh
1394 Open Host Controller Specification, Rev. 1.1, Section 6.4
DCh
0000 0000h
1394 Open Host Controller Specification, Rev. 1.1, Section 5.9
A8h set register
RW This field specifies the maximum number of priority arbitration requests for asyn-
R
(continued)
Reserved. Bits 31:8 return 0s when read.
chronous request packets that the link is permitted to make of the PHY core during
the fairness interval.
1394a PCI PHY/Link Open Host Controller
Description
FW322 06 T100
55