l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet - Page 7

• Manufacturer Part Number: l-fw32206t100
• Description: 1394a Phy/link Open Host Controller
• Manufacturer: ETC-unknow

Data Sheet, Rev. 1
December 2005
FW322 Functional Description
The FW322 is comprised of four major functional sections (see Figure 1): PCI core, OHCI isochronous and
asynchronous data transfer, link core, and PHY core. The following is a general description of each of the major
sections.
PCI Core
The PCI core (shown in Figure 2) serves as the interface to the PCI bus. It contains the state machines that allow
the FW322 to respond properly when it is the target of the transaction. Also, during 1394 packet transmission or
reception, the PCI core arbitrates for the PCI bus and enables the FW322 to become the bus master for reading the
different buffer descriptors and management of the actual data transfers to/from host system memory.
The PCI core also supports the PCI Bus Power Management Interface Specification v.1.1. Included in this support
is a standard power management register interface accessible through the PCI configuration space. Through this
register interface, software is able to transition the FW322 into four distinct power consumption states (D0, D1, D2,
and D3hot). This permits software to selectively increase/decrease the power consumption of the FW322 for
reasons such as periods of system inactivity or power conservation. In addition, the FW322 also includes support
for waking up the system through the generation of a power management event (PME).
The FW322 supports generation of a power management event (PME) while in the D0, D1, D2, and D3hot power
states.
Agere Systems Inc.
PCI BUS
Figure 2. PCI Core Block Diagram
CONFIGURATION
ADDRESS/DATA
MUX
PCI
1394a PCI PHY/Link Open Host Controller
CONTROL
CONTROL
MASTER
SLAVE
PCI SLAVE
PCI MASTER
FW322 06 T100
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