l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet - Page 75

• Manufacturer Part Number: l-fw32206t100
• Description: 1394a Phy/link Open Host Controller
• Manufacturer: ETC-unknow

Data Sheet, Rev. 1
December 2005
Internal Register Configuration
The meaning of the register fields in the port status page are defined by Table 67 below.
Table 67. PHY Core Register Port Status Page Fields
Agere Systems Inc.
Negotiated_speed
Connected
Int_enable
Disabled
AStat
BStat
Field
Child
Fault
Bias
Size Type
2
2
1
1
1
1
3
1
1
RW
RW
RW
R
R
R
R
R
R
Power Reset
Value
000
—
—
0
0
0
0
0
0
(continued)
TPA line state for the port:
00
01
10
11
TPB line state for the port (same encoding as AStat).
If this bit is equal to one, the port is a child; otherwise, a par-
ent. The meaning of this bit is undefined from the time a bus
reset is detected until the PHY core transitions to state T1:
child handshake during the tree identify process (see Section
4.4.2.2 in IEEE Standard 1394a-2000).
If equal to one, the port is connected.
If equal to one, incoming TPBIAS is detected.
If equal to one, the port is disabled.
Indicates the maximum speed negotiated between this PHY
core port and its immediately connected port; the encoding is
the same as for the PHY Core Register Max_speed field (see
Table 65).
Enable Port Event Interrupts. When set to one, the PHY
core will set Port_event to one if any of connected, bias, dis-
abled, or fault (for this port) change state.
Set to one if an error is detected during a suspend or resume
operation. A write of one to this bit clears it to zero.
2
2
2
2
= Z.
= invalid.
= 1.
= 0.
1394a PCI PHY/Link Open Host Controller
Description
FW322 06 T100
75