l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet - Page 44

• Manufacturer Part Number: l-fw32206t100
• Description: 1394a Phy/link Open Host Controller
• Manufacturer: ETC-unknow

FW322 06 T100
1394a PCI PHY/Link Open Host Controller
Internal Registers
Host Controller Control Register
The Host Controller Control set/clear register pair provides flags for controlling the OHCI portion of the FW322.
Offset:
Default:
Reference:
Table 34. Host Controller Control Register Description
44
44
28:24
21:20
Bit
31
30
29
23
22
19
18
aPhyEnhanceEnable
programPhyEnable
postedWriteEnable
noByteSwapData
ackTardyEnable
1394 Open Host Controller Interface Specification, Rev. 1.1, Section 5.7
50h set register
54h clear register
X08X 0000h
BIBimageValid
Field Name
Reserved
Reserved
LPS
(continued)
Type
RSU
RSC
RSC
RSC
RSU
RSC
RC
R
R
This bit is used to enable both OHCI response to block read
requests to host configuration ROM and the OHCI mechanism for
automatically updating configuration ROM. When this bit is 0, the
OHCI returns a ack_type_error on block read requests to configu-
ration ROM and does not update the configROMmap register or
ConfigROMheader and BusOptions registers when a 1394 bus
reset occurs. When this bit is 1, the physical response unit handles
block reads of host configuration ROM and the mechanism for
automatically updating configuration ROM is enabled.
This bit is used to control byte swapping during host bus accesses
involving the data portion of 1394 packets. Data is swapped if
equal to 0, not swapped when equal to 1.
This bit is used to control the acknowledgment of ack_tardy. When
this bit is set to one, ack_tardy may be returned as an acknowl-
edgement to configuration ROM accesses from 1394 to OHCI
including accesses to the bus_info_block. The host controller will
return ack_tardy to all other asynchronous packets addressed to
the OHCI node.
Reserved. Bits 28:24 return 0s when read.
This bit informs upper-level software that lower-level software has
consistently configured the 1394a-2000 enhancements in the link
and PHY core. When this bit is 1, generic software such as the
OHCI driver is responsible for configuring 1394a-2000 enhance-
ments in the PHY core and bit 22 (aPhyEnhanceEnable) in the
FW322. When this bit is 0, the generic software may not modify
the 1394a-2000 enhancements in the FW322 and cannot interpret
the setting of bit 22 (aPhyEnhanceEnable). When a serial
EEPROM is present, this bit is initialized from the EEPROM.
Otherwise, this bit is initialized to the hardware default value.
When bits 23 (programPhyEnable) is 1 and 17 (linkEnable) is 0,
the OHCI driver can set this bit to use all 1394a-2000 enhance-
ments. When bit 23 (programPhyEnable) is set to 0, the software
does not change PHY enhancements or this bit.
Reserved. Bits 21:20 return 0s when read.
Link Power Status. This bit drives the LPS signal to the PHY core
within the FW322 (see Section 5.7 of the OHCI 1.1 Specification
for additional details).
This bit is used to enable (1) or disable (0) posted writes. Software
should change this bit only when bit 17 (linkEnable) is 0.
Description
Data Sheet, Rev. 1
December 2005
Agere Systems Inc.