l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet - Page 48

• Manufacturer Part Number: l-fw32206t100
• Description: 1394a Phy/link Open Host Controller
• Manufacturer: ETC-unknow

FW322 06 T100
1394a PCI PHY/Link Open Host Controller
Internal Registers
Interrupt Event (IntEvent) Register
The Interrupt Event set/clear register reflects the state of the various FW322 interrupt sources. The interrupt bits
are set by an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the
set register. The only mechanism to clear the bits in this register is to write a 1 to the corresponding bit in the clear
register. Reading the IntEventSet register returns the current state of the IntEvent register. Reading the
IntEventClear register returns the masked version of the IntEvent register, i.e., the bit-wise AND function of
IntEvent and IntMask.
Offset:
Default:
Reference:
Table 39. Interrupt Event Register Description
48
48
Bit
31
30
29
28
27
26
25
24
23
22
unrecoverableError
cycleInconsistent
vendorSpecific
cycleTooLong
phyRegRcvd
80h set register
84h clear register
XXXX 0XXXh
1394 Open Host Controller Interface Specification, Rev. 1.1, Section 6.1.
SoftInterrupt
Field Name
ack_Tardy
Reserved
Reserved
cycleLost
(continued)
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
Type
RSC
R
R
Reserved. Bit 31 returns 0 when read.
This vendor-specific interrupt event is reported when serial EEPROM
read is complete.
Soft Interrupt. This bit may be used by software to generate a host
controller interrupt for its own use.
Reserved. Bit 28 returns 0 when read.
This bit will be set when the ackTardyEnable bit of the HC Control
register (see Table 34) is set to 1 and any of the following conditions
occur:
a. Data is present in a FIFO that is to be delivered to the host.
b. The physical response unit is busy processing requests or sending
c. The host controller sent an ack_tardy acknowledgment.
The FW322 has received a PHY Core register data byte, which can be
read from the PHY Core Layer Control register.
If bit 21 (cycleMaster) of the Link Control register (see Table 45) is set,
then this indicates that over 125 µs have elapsed between the start of
sending a cycle start packet and the end of a subaction gap. The Link
Control register bit 21 (cycleMaster) is cleared by this event.
This event occurs when the FW322 encounters any error that forces it
to stop operations on any or all of its subunits, for example, when a
DMA context sets its dead bit. While this bit is set, all normal interrupts
for the context(s) that caused this interrupt are blocked from being set.
A cycle start was received that had values for cycleSeconds and
cycleCount fields that are different from the values in bits 31:25 (cycle-
Seconds field) and bits 24:12 (cycleCount field) of the Isochronous
Cycle Timer register (see Table 48).
A lost cycle is indicated when no cycle_start packet is sent/received
between two successive cycleSynch events. A lost cycle can be
predicted when a cycle_start packet does not immediately follow the
first subaction gap after the cycleSynch event or if an arbitration reset
gap is detected after a cycleSynch event without an intervening cycle
start. This bit may be set either when it occurs or when logic predicts
that it will occur.
responses.
Description
Data Sheet, Rev. 1
December 2005
Agere Systems Inc.