l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet - Page 56

• Manufacturer Part Number: l-fw32206t100
• Description: 1394a Phy/link Open Host Controller
• Manufacturer: ETC-unknow

FW322 06 T100
1394a PCI PHY/Link Open Host Controller
Internal Registers
Link Control Register
The Link Control register provides flags to enable and configure the link core cycle timer and receiver portions of
the FW322.
Offset:
Default:
Reference:
Table 45. Link Control Register Description
56
56
31:23
19:11
Bit
8:7
5:0
22
21
20
10
9
6
tag1SyncFilterLock
CycleTimerEnable
E0h set register
E4h clear register
00X0 0X00h
1394 Open Host Controller Specification, Rev. 1.1, Section 5.10
cycleSource
Field Name
cycleMaster
RcvPhyPkt
RcvSelfID
Reserved
Reserved
Reserved
Reserved
(continued)
RSCU
Type
RSC
RSC
RSC
RSC
RS
R
R
R
R
Reserved. Bits 31:23 return 0s when read.
Set to 0, since the FW322 does not support an external cycle
timer.
When this bit is set, and the FW322 PHY core has notified the
OHCI core that it is root, the OHCI generates a cycle start packet
every time the cycle timer rolls over, based on the setting of bit 22.
When this bit is cleared, the OHCI accepts received cycle start
packets to maintain synchronization with the node that is sending
them. This bit is automatically reset when bit 25 (cycleTooLong) of
the Interrupt Event register (see Table 39) is set and cannot be set
until bit 25 (cycleTooLong) is cleared.
When this bit is set, the cycle timer offset counts cycles of the
24.576 MHz clock and rolls over at the appropriate time based on
the settings of the above bits. When this bit is cleared, the cycle
timer offset does not count.
Reserved. Bits 19:11 return 0s when read.
When this bit is set, the receiver accepts incoming PHY core
packets into the AR request context if the AR request context is
enabled. This does not control receipt of self-identification packets
received outside of the SelfID phase of bus initialization.
When this bit is set, the receiver accepts incoming self-identifica-
tion packets. Before setting this bit to 1, software must ensure that
the SelfID Buffer Pointer register contains a valid address.
Reserved.
When this bit is set, the tag1SyncFilter bit of the IR Context Match
register (see Table 59) equals one for all IR contexts. When this bit
is cleared, the tag1SynchFilter bit has read/write access. A hard-
ware reset clears this bit to 0. A soft reset has no effect.
Reserved. Bits 5:0 return 0s when read.
Description
Data Sheet, Rev. 1
December 2005
Agere Systems Inc.