l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet - Page 13

• Manufacturer Part Number: l-fw32206t100
• Description: 1394a Phy/link Open Host Controller
• Manufacturer: ETC-unknow

Data Sheet, Rev. 1
December 2005
FW322 Functional Description
PHY Core
The PHY core in Figure 5 on the preceding page pro-
vides the analog physical layer functions needed to
implement a two-port node in a cable-based IEEE
1394 -1995 and IEEE 1394 a-2000 network.
Each cable port incorporates two differential line trans-
ceivers. The transceivers include circuitry to monitor
the line conditions as needed for determining connec-
tion status, for initialization and arbitration, and for
packet reception and transmission. The PHY core
interfaces with the link core.
The PHY core requires either an external 24.576 MHz
crystal or crystal oscillator. The internal oscillator
drives an internal phase-locked loop (PLL), which gen-
erates the required 393.216 MHz reference signal. The
393.216 MHz reference signal is internally divided to
provide the 49.152 MHz, 98.304 MHz, and
196.608 MHz clock signals that control transmission of
the outbound encoded strobe and data information.
The 49.152 MHz clock signal is also supplied to the
associated link layer controller (LLC) for synchroniza-
tion of the link with the PHY core and is used for
resynchronization of the received data.
The PHY/link interface is a direct connection and does
not provide isolation.
Data bits to be transmitted through the cable ports are
received from the LLC on two, four, or eight data lines
(D[0:7]), and are latched internally in the PHY in syn-
chronization with the 49.152 MHz system clock. These
bits are combined serially, encoded, and transmitted at
98.304 Mbits/s, 196.608 Mbits/s, or 393.216 Mbits/s as
the outbound data-strobe information stream. During
transmission, the encoded data information is transmit-
ted differentially on the TPA and TPB cable pair(s).
During packet reception, the TPA and TPB transmit-
ters of the receiving cable port are disabled, and the
receivers for that port are enabled. The encoded data
information is received on the TPA and TPB cable pair.
The received data strobe information is decoded to
recover the receive clock signal and the serial data
bits. The serial data bits are split into two (for S100),
four (for S200), or eight (for S400) parallel streams,
resynchronized to the local system clock, and sent to
the associated LLC. The received data is also transmit-
ted (repeated) out of the other active (connected) cable
ports.
Agere Systems Inc.
(continued)
Both the TPA and TPB cable interfaces incorporate
differential comparators to monitor the line states dur-
ing initialization and arbitration. The outputs of these
comparators are used by the internal logic to deter-
mine the arbitration status. The TPA channel monitors
the incoming cable common-mode voltage. The value
of this common-mode voltage is used during arbitra-
tion to set the speed of the next packet transmission.
In addition, the TPB channel monitors the incoming
cable common-mode voltage for the presence of the
remotely supplied twisted-pair bias voltage. This
monitor is called bias-detect.
The TPBIAS circuit monitors the value of incoming
TPA pair common-mode voltage when local TPBIAS is
inactive. Because this circuit has an internal current
source and the connected node has a current sink, the
monitored value indicates the cable connection status.
The monitor is called connect-detect.
Both the TPB bias-detect monitor and TPBIAS
connect-detect monitor are used in suspend/resume
signaling and cable connection detection.
The PHY core provides a 1.86 V nominal bias voltage
for driver load termination. This bias voltage, when
seen through a cable by a remote receiver, indicates
the presence of an active connection. The value of this
bias voltage has been chosen to allow interoperability
between transceiver chips operating from 5 V or 3 V
nominal supplies. This bias voltage source should be
stabilized by using an external filter capacitor of
approximately 0.33 µF.
The port transmitter circuitry and the receiver circuitry
are disabled when the port is disabled, suspended, or
disconnected.
The line drivers in the PHY core operate in a high-
impedance current mode and are designed to work
with external 112 Ω line-termination resistor networks.
One network is provided at each end of each twisted-
pair cable. Each network is composed of a pair of
series-connected 56 Ω resistors. The midpoint of the
pair of resistors that is directly connected to the
twisted-pair A (TPA) signals is connected to the
TPBIAS voltage signal. The midpoint of the pair of
resistors that is directly connected to the twisted-pair B
(TPB) signals is coupled to ground through a parallel
RC network with recommended resistor and capacitor
values of 5 kΩ and 220 pF, respectively. The values of
the external resistors are specified to meet the 1394a-
2000 Specification when connected in parallel with the
internal receiver circuits.
1394a PCI PHY/Link Open Host Controller
FW322 06 T100
13