l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet - Page 41

• Manufacturer Part Number: l-fw32206t100
• Description: 1394a Phy/link Open Host Controller
• Manufacturer: ETC-unknow

Data Sheet, Rev. 1
December 2005
Internal Registers
GUID High Register
The GUID High register represents the upper quadlet in a 64-bit global unique ID (GUID), which maps to the third
quadlet in the Bus_Info_Block 1394, addressable at FFFF_F000_0410. This register contains node_vendor_ID
and chip_ID_hi fields. This register initializes to 0s on a hardware reset, which is an illegal GUID value. If a serial
EEPROM is detected, then the contents of this register are loaded through the serial EEPROM interface after a
PCI reset. If no serial EEPROM is detected, then the contents of this register can be loaded with a single PCI
write to either of two configuration registers, executed after a PCI reset. The two configuration registers are
located at offset 0x70, for new PCI applications, and offset 0x80, for backward compatibility with FW322 05 PCI
applications only. After one of these load mechanisms has completed, this register becomes read only.
Offset:
Default:
Reference:
Table 28. GUID High Register Description
GUID Low Register
The GUID Low register represents the lower quadlet in a 64-bit global unique ID (GUID), which maps to
chip_ID_lo in the Bus_Info_Block 1394, addressable at FFFF_F000_0414. This register initializes to 0s on a
hardware reset and behaves identical to the GUID High register. If no serial EEPROM is detected, then the
contents of this register can be loaded with a PCI configuration write to either offset 0x74 or 0x84, as described
above.
Offset:
Default:
Reference:
Table 29. GUID Low Register Description
Agere Systems Inc.
31:8
31:0
Bit
7:0
Bit
node_vendor_ID
1394 Open Host Controller Interface Specification, Rev. 1.1, Section 5.5.5
1394 Open Host Controller Interface Specification, Rev. 1.1, Section 5.5.5
0000 0000h
0000 0000h
24h
28h
Field Name
Field Name
chip_ID_hi
chip_ID_lo
(continued)
RWU
RWU
Type
Type
R
IEEE 1394 Bus Management Fields. Firmware or hardware must
ensure that this register is valid whenever HCCControl.linkEnable
bit is set.
Firmware or hardware must ensure that this register is valid when-
ever HCCControl.linkEnable bit is set.
IEEE 1394 Bus Management Fields. Firmware or hardware must
ensure that this register is valid whenever HCCControl.linkEnable
bit is set.
1394a PCI PHY/Link Open Host Controller
Description
Description
FW322 06 T100
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