l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet - Page 45

• Manufacturer Part Number: l-fw32206t100
• Description: 1394a Phy/link Open Host Controller
• Manufacturer: ETC-unknow

Data Sheet, Rev. 1
December 2005
Internal Registers
Table 34. Host Controller Control Register Description (continued)
Agere Systems Inc.
15:0
Bit
17
16
Field Name
linkEnable
SoftReset
Reserved
(continued)
Type
RSU
RSU
R
This bit is cleared to 0 by either a hardware or software reset. Soft-
ware must set this bit to 1 when the system is ready to begin oper-
ation and then force a bus reset. This bit is necessary to keep
other nodes from sending transactions before the local system is
ready. When this bit is cleared, the FW322 is logically and immedi-
ately disconnected from the 1394 bus, no packets are received or
processed, and no packets transmitted.
When this bit is set, all FW322 states are reset, all FIFOs are
flushed, and all OHCI registers are set to their hardware reset
values unless otherwise specified. PCI registers are not affected
by this bit. This bit remains set while the softReset is in progress
and reverts back to 0 when the reset has completed.
Reserved. Bits 15:0 return 0s when read.
1394a PCI PHY/Link Open Host Controller
Description
FW322 06 T100
45