l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet - Page 25

• Manufacturer Part Number: l-fw32206t100
• Description: 1394a Phy/link Open Host Controller
• Manufacturer: ETC-unknow

Data Sheet, Rev. 1
December 2005
Internal Registers
Class Code and Revision ID Registers
The Class Code register and Revision ID register categorize the FW322 as a serial bus controller (0Ch),
controlling an IEEE 1394 bus (00h), with an OHCI programming model (10h). Furthermore, the chip revision is
indicated in the lower byte.
Offset:
Default:
Type:
Reference:
Table 6. Class Code and Revision ID Register Description
* x is a minor revision number of the FW322 06 T100 and may be any value from 0 hex to F hex.
Latency Timer and Cache Line Size Register
The Latency Timer and Class Cache Line Size register is programmed by host BIOS to indicate system cache line
size and the latency timer associated with the FW322. If a serial EEPROM is detected, then the contents of this
register are loaded from the serial EEPROM interface after a PCI reset. If no serial EEPROM is detected, then this
register returns a default value of 0000h.
Offset:
Default:
Type:
Reference:
Table 7. Latency Timer and Class Cache Line Size Register Description
Agere Systems Inc.
31:24
23:16
15:8
15:8
Bit
7:0
Bit
7:0
LATENCY_TIMER
CACHELINE_SZ
BASECLASS
Field Name
SUBCLASS
CHIPREV
0C00 106xh*
PCI Local Bus Specification, Rev. 2.2, Section 6.2.1 and 1394 Open Host Controller Interface
Specification, Rev. 1.1, Section A.3.3 and A.3.4.
0Ch
0000h
PCI Local Bus Specification, Rev. 2.2, Section 6.2.4
08h
Read only
Read/write
Field Name
PGMIF
(continued)
Type
R
R
R
R
Type
RW
RW
Base Class. This field returns 0Ch when read, which classifies the func-
tion as a serial bus controller.
Subclass. This field returns 00h when read, which specifically classifies
the function as an IEEE 1394 serial bus controller.
Programming Interface. This field returns 10h when read, indicating
that the programming model is compliant with the 1394 Open Host
Controller Interface Specification.
Silicon Revision. This field returns 6xh* when read, indicating the
silicon revision of the FW322.
PCI Latency Timer. The value in this register specifies the latency
timer, in units of PCI clock cycles, for the FW322. When the FW322 is
a PCI bus initiator and asserts FRAME, the latency timer begins
counting from zero. If the latency timer expires before the FW322
transaction has terminated, then the FW322 terminates the transac-
tion when its PCI_GNTN is deasserted.
Cache Line Size. This value is used by the FW322 during memory
write and invalidate, memory read line, and memory read multiple
transactions.
1394a PCI PHY/Link Open Host Controller
Description
Description
FW322 06 T100
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