l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet - Page 58

• Manufacturer Part Number: l-fw32206t100
• Description: 1394a Phy/link Open Host Controller
• Manufacturer: ETC-unknow

FW322 06 T100
1394a PCI PHY/Link Open Host Controller
Internal Registers
PHY Core Layer Control Register
The PHY Core Layer Control register is used to read or write a PHY Core register.
Offset:
Default:
Reference:
Table 47. PHY Core Layer Control Register Description
Isochronous Cycle Timer Register
The Isochronous Cycle Timer register indicates the current cycle number and offset. When the FW322 is cycle
master, this register is transmitted with the cycle start message. When the FW322 is not cycle master, this register
is loaded with the data field in an incoming cycle start. In the event that the cycle start message is not received, the
fields can continue incrementing on their own (if programmed) to maintain a local time reference.
Offset:
Default:
Reference:
Table 48. Isochronous Cycle Timer Register Description
58
58
30:28
27:24
23:16
13:12
31:25
24:12
11:8
Bit
7:0
11:0
31
15
14
Bit
Field Name
Reserved
Reserved
cycleSeconds
regAddr
rdDone
wrData
rdAddr
rdData
Field Name
wrReg
rdReg
cycleCount
cycleOffset
ECh
0000 0000h
1394 Open Host Controller Specification, Rev. 1.1, Section 5.12
F0h
XXXX XXXXh
1394 Open Host Controller Specification, Rev. 1.1, Section 5.13
(continued)
RWU This bit is set by software to initiate a read request to a PHY Core register and is
RWU This bit is set by software to initiate a write request to a PHY Core register and is
Type
RW
RW
RU
RU
RU
R
R
RWU This field counts seconds [rollovers from bits 24:12 (cycleCount field)]
RWU This field counts cycles [rollovers from bits 11:0 (cycleOffset field)] modulo
RWU This field counts 24.576 MHz clocks modulo 3072, i.e., 125 ms. If an
Type
This bit is cleared to 0 by the FW322 when either bit 15 (rdReg) or bit 14 (wrReg)
is set. This bit is set when a register transfer is received by the OHCI core from
the PHY core and rdData is updated.
Reserved. Bits 30:28 return 0s when read.
This is the address of the register most recently received from the PHY core.
This field is the contents of a PHY Core register, which have been read at rdAddr.
cleared by hardware when the request has been sent. Bit 14 (wrReg) must not be
set when bit 15 (rdReg) is set.
cleared by hardware when the request has been sent. Bit 15 (rdReg) must not be
set when bit 14 (wrReg) is set.
Reserved. Bits 13:12 return 0s when read.
This field is the address of the PHY Core register to be written or read.
This field is the data to be written to a PHY Core register and is ignored for reads.
modulo 128.
8000.
external 8 kHz clock configuration is being used, then this bit must be set to
0 at each tick of the external clock.
Description
Description
Data Sheet, Rev. 1
December 2005
Agere Systems Inc.