l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet - Page 50

• Manufacturer Part Number: l-fw32206t100
• Description: 1394a Phy/link Open Host Controller
• Manufacturer: ETC-unknow

FW322 06 T100
1394a PCI PHY/Link Open Host Controller
Internal Registers
Interrupt Mask (IntMask) Register
The Interrupt Mask set/clear register is used to enable/disable the various FW322 interrupt sources. Reads from
either the set register or the clear register always return the contents of the Interrupt Mask register. In all cases
except masterIntEnable (bit 31), the enables for each interrupt event align with the Interrupt Event (IntEvent)
register bits (see Table 39). A one bit in the IntMask register enables the corresponding IntEvent register bit to
generate a processor interrupt. A zero bit in IntMask disables the corresponding IntEvent register bit from
generating a processor interrupt. A bit is set in the IntMask register by writing a one to the corresponding bit in the
IntMaskSet address and cleared by writing a one to the corresponding bit in the IntMaskClear address.
Offset:
Default:
Reference:
Table 40. Interrupt Mask Register Description
50
50
14:10
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
unrecoverableError
cycleInconsistent
SelfIDcomplete2
masterIntEnable
cycle64Seconds
88h
8Ch clear register
XXXX 0XXXh
1394 Open Host Controller Interface Specification, Rev. 1.1, Section 6.2.
selfIDcomplete
vendorSpecific
regAccessFail
cycleTooLong
phyRegRcvd
Field Name
softInterrupt
cycleSynch
ack_Tardy
Reserved
busReset
Reserved
cycleLost
PHY
set register
(continued)
RSCU
RSCU
Type
RSC
RSC
R
R
Master Interrupt Enable. If this bit is set, then external interrupts
are generated in accordance with the Interrupt Mask register. If this
bit is cleared, then external interrupts are not generated, regardless
of the Interrupt Mask register settings. The value of masterIntEnable
has no effect on the value returned by reading the IntEventClear.
When this bit is set, this vendor-specific interrupt mask enables
interrupt generation when bit 30 (vendorSpecific) of the Interrupt
Event register (Table 39) is set.
Soft Interrupt. This bit may be used by software to generate a host
controller interrupt for its own use. When set, this bit enables the
corresponding IntEvent register bit to generate a processor inter-
rupt.
Reserved. Bit 28 returns 0 when read.
A one bit enables the corresponding IntEvent register bit to
generate a processor interrupt. A zero bit disables the
corresponding IntEvent register bit from generating a processor
interrupt.
Reserved. Bits 14:10 return 0s when read.
Description
Data Sheet, Rev. 1
December 2005
Agere Systems Inc.