l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet - Page 61

• Manufacturer Part Number: l-fw32206t100
• Description: 1394a Phy/link Open Host Controller
• Manufacturer: ETC-unknow

Data Sheet, Rev. 1
December 2005
Internal Registers
Asynchronous Context Control Register
The Asynchronous Context Control set/clear register controls the state and indicates status of the DMA context.
Offset:
Default:
Reference:
Table 53. Asynchronous Context Control Register Description
Agere Systems Inc.
31:16
14:13
9:8
7:5
4:0
Bit
15
12
10
11
(Note: These bits are
reserved, undefined
for the ATRQ and
ATRS contexts.)
Field Name
eventcode
184h
1A0h
1A4h
1C0h
1C4h
1E0h
1E4h
0000 X0XXh
1394 Open Host Controller Specification, Rev. 1.1, Section 7.22, 8.3.2, 3.1.1
Reserved
Reserved
Reserved
180h
active
wake
dead
spd
run
(continued)
set register (ATRQ)
clear register (ATRQ)
set register (ATRS)
clear register (ATRS)
set register (ARRQ)
clear register (ARRQ)
set register (ARRS)
clear register (ARRS)
RSCU
Type
RSU
RU
RU
RU
RU
R
R
R
Reserved. Bits 31:16 return 0s when read.
This bit is set by software to enable descriptor processing for the
context and cleared by software to stop descriptor processing. The
FW322 changes this bit (i.e., sets it to 0) only on a hardware or soft-
ware reset.
Reserved. Bits 14:13 return 0s when read.
Software sets this bit to cause the FW322 to continue or resume
descriptor processing. The FW322 clears this bit on every descriptor
fetch.
The FW322 sets this bit when it encounters a fatal error and clears the
bit when software resets bit 15 (run).
The FW322 sets this bit to 1 when it is processing descriptors.
Reserved. Bits 9:8 return 0s when read.
This field indicates the speed at which a packet was received or trans-
mitted, and only contains meaningful information for receive contexts.
This field is encoded as:
000 = 100 Mbits/s.
001 = 200 Mbits/s.
010 = 400 Mbits/s.
All other values are reserved. Software should not attempt to interpret
the contents of this field while the active or wake bits are set.
This field holds the acknowledge sent by the link core for this packet or
an internally generated error code if the packet was not transferred
successfully.
1394a PCI PHY/Link Open Host Controller
Description
FW322 06 T100
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