l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet - Page 70

• Manufacturer Part Number: l-fw32206t100
• Description: 1394a Phy/link Open Host Controller
• Manufacturer: ETC-unknow

FW322 06 T100
1394a PCI PHY/Link Open Host Controller
Internal Registers
Link Options
The values in this register provide low-level control of configurable features within the FW322 that are beyond
those stated in 1394 and OHCI specifications.
Offset:
Default:
Table 63. Link Options Register Description
70
70
19:6
Bits
5:3
2:0
31
30
29
28
27
26
25
24
23
22
21
20
ConfigROMEnable Enables config ROM management, including config ROM block reads, as defined
RegAccessFailEn Enables RegAccessFailEn interrupt for SCLK register accesses that fail.
DualBufferEnable Enables IR dual-buffer mode processing as defined in OHCI 1.1
ITChangeEnable
Posted Writes
InitBMEnable
RetryEnable
Cycle Timer
OHCI1.1En
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Control
840h
0000 0020h
Field
(continued)
Enables general features of OHCI 1.1 that are not covered by any of the bits below.
Reserved for internal use by the FW322. Must be set to 0x0.
Enables usage of initial registers for loading Bus Management registers on a bus
reset.
Enables retry processing as defined in OHCI 1.1.
in OHCI 1.1.
Enables skip and FIFO underrun processing in the IT context as defined in
OHCI 1.1.
Reserved for internal use by the FW322. Must be set to 0x0.
Read-only status bit. Reserved for internal use by the FW322. Will read back as
0x0.
Reserved for internal use by the FW322. Must be set to 0x0.
Reserved for internal use by the FW322. Must be set to 0x0.
Reserved for internal use by the FW322. Must be set to 0x0.
Number of physical posted writes the link is allowed to queue in the asynchronous
receive FIFO. These three bits [5:3] default to 100b, which is the maximum value.
Values greater than 100b will disable all physical posted writes.
Selects the value the FW322 will use for its isochronous cycle period when the
FW322 is the root node. This value is for debugging purposes only and should not
be set to any value other than its default value in a real 1394 network. This value
defaults to 0.
If 0, cycle = 125 µs.
If 1, cycle = 62.5 µs.
If 2, cycle = 31.25 µs.
If 3, cycle = 15.625 µs.
If 4, cycle = 7.8125 µs.
Description
Data Sheet, Rev. 1
December 2005
Agere Systems Inc.