l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet - Page 31

• Manufacturer Part Number: l-fw32206t100
• Description: 1394a Phy/link Open Host Controller
• Manufacturer: ETC-unknow

Data Sheet, Rev. 1
December 2005
Internal Registers
Power Management Control and Status Register
The Power Management Control and Status register implements the control and status of the PCI power manage-
ment function. This register is not affected by the internally generated reset caused by the transition from the D3hot
to D0 state. All bits within this register, will be reset by a PCI reset.
Offset:
Default:
Type:
Reference:
Table 16. Power Management Control and Status Register Description
Agere Systems Inc.
14:13
12:9
Bit
7:5
3:2
1:0
15
8
4
XX00h
Read/write
PCI Bus Power Management Interface Specification, Rev. 1.1, Section 3.2.4 and 1394 Open Host
Controller Interface Specification, Rev. 1.1, Section A.3.8.4
48h
DATA_SELECT
DATA_SCALE
PWR_STATE
Field Name
DYN_DATA
PME_ENB
PME_STS
Reserved
Reserved
(continued)
Type
RW PME Enable. This bit enables the function to assert PME. If this bit is
RW Power State. This 2-bit field is used to set the FW322 device power
RC This bit is set when the FW322 would normally be asserting the PME
R
R
R
R
R
signal, independent of the state of the PME_ENB bit. This bit is
cleared by a writeback of 1, and this also clears the PME signal driven
by the FW322. Writing a 0 to this bit has no effect.
This 2-bit field indicates a scaling factor that is to be used when inter-
preting the value of the PM_DATA register within the Power Manage-
ment Extension register. The value and meaning of this field will vary
depending on the value that has been selected by the DATA_SELECT
field.
This 4-bit field is used to select which data values are to be reported
through the PM_DATA field in the Power Management Extension
register and the DATA_SCALE fields. Valid values are 0—7, which
map to power consumption/dissipation ratings for the FW322 within
the PM_DATA/DATA_SCALE fields.
cleared, then assertion of PME is disabled.
Reserved. Bits 7:5 return 0s when read.
Dynamic Data. This bit returns 0 when read, since the FW322 does
not report dynamic data.
Reserved. Bits 3:2 return 0s when read.
state and is encoded as follows:
00 = current power state is D0.
01 = current power state is D1.
10 = current power state is D2.
11 = current power state is D3.
1394a PCI PHY/Link Open Host Controller
Description
FW322 06 T100
31