l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet - Page 47

• Manufacturer Part Number: l-fw32206t100
• Description: 1394a Phy/link Open Host Controller
• Manufacturer: ETC-unknow

Data Sheet, Rev. 1
December 2005
Internal Registers
Isochronous Receive Multiple Channel Mask High (IRMultiChanMaskHi) Register
The Isochronous Receive Multiple Channel Mask High set/clear register is used to enable packet receives from
the upper 32 isochronous data channels. A read from either the set register or clear register returns the content of
the Isochronous Receive Multiple Channel Mask High register.
Offset:
Default:
Reference:
Table 37. Isochronous Receive Channel Mask High Register Description
Isochronous Receive Multiple Channel Mask Low (IRMultiChanMaskLo) Register
The Isochronous Receive Channel Mask Low set/clear register is used to enable packet receives from the lower
32 isochronous data channels.
Offset:
Default:
Reference:
Table 38. Isochronous Receive Channel Mask Low Register Description
Agere Systems Inc.
31:0 isoChannel(N + 32)
31:0
Bit
Bit
isoChannel N
Field Name
Field Name
74h clear register
XXXX XXXXh
1394 Open Host Controller Interface Specification, Rev. 1.1, Section 10.4.1.1
7Ch clear register
XXXX XXXXh
1394 Open Host Controller Interface Specification, Rev. 1.1, Section 10.4.1.
70h set register
78h set register
(continued)
Type
Type
RSC
RSC
If bit N (where N = a bit number 0—31) is set, iso
channel number (N + 32) is enabled.
If bit N (where N = a bit number 0—31) is set, iso
channel number N is enabled.
Description
Description
1394a PCI PHY/Link Open Host Controller
FW322 06 T100
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