l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet - Page 69

• Manufacturer Part Number: l-fw32206t100
• Description: 1394a Phy/link Open Host Controller
• Manufacturer: ETC-unknow

Data Sheet, Rev. 1
December 2005
Internal Registers
Asynchronous DMA Control
The fields in this register control the functionality within the asynchronous and physical DMA engines. Accesses to
the PCI bus and how much data the DMA engines will attempt to move in a single PCI transaction can be con-
trolled. The actual PCI burst sizes will also be affected by 1394 packet size, host memory buffer size, FIFO con-
straints, and the PCI cache line size.
Offset:
Default:
Table 62. Asynchronous DMA Control Registers Description
Agere Systems Inc.
23:16
15:12
11:8
Bits
7:4
3:0
24
AR Maximum Burst The maximum number of quadlets that will be written by the AR and physical
AT FIFO Threshold This field defines the number of quadlets of packet data that must be available
AT Maximum Burst The maximum number of quadlets that will be fetched by the AT or physical
Retry Threshold
0010 7373h
AR Threshold
808h
AT Threshold
Max. Enable
Field
(continued)
When this bit is set, a packet being retried, e.g., due to an ack_busy on the
initial attempt, will behave as if the AT FIFO threshold value was set to the
maximum (n = 0x20). The purpose of this feature is to prevent a packet that
previously experienced a FIFO underrun on the initial transmit attempt from
failing again due to a FIFO underrun on the retry attempt. If this bit is not set,
retried packets will use the same AT FIFO threshold as the initial transmit
attempt. The default value of this field is 0x0.
in the AT FIFO before the link will be notified that there is an asynchronous
packet to be transmitted. (The link will also be signaled that a packet is available
for transmission if the entire packet is in the FIFO, regardless of its size.) The
threshold is 16 * n quadlets; n defaults to a value of 0x10 (256 quadlets). Max
size of n is 0x20 (512 quadlets).
read response DMAs in one PCI transaction. The maximum burst is 16 * (n + 1)
quadlets; n defaults to 7 (128 quadlets). Max value of n is 0xf.
This field defines the amount of available space that is needed in the AT FIFO,
before the AT or physical read response units will request access to the PCI
bus. The threshold is 16 * (n + 1) quadlets; n defaults to 0 (16 quadlets). Note,
however, that the AT or physical DMAs may request access to the PCI bus
sooner if the amount of data to be fetched from memory is less than the amount
of space available in the AT FIFO. Max value of n is 0xf.
write DMAs in one PCI transaction. The maximum burst is 16 * (n + 1) quadlets;
n defaults to 7 (128 quadlets). Max value of n is 0xf.
This field defines the amount of available data that is needed in the AR FIFO,
before the AR DMA will request access to the PCI bus. The threshold is
16 * (n + 1) quadlets; n defaults to 0 (16 quadlets). However, the AR DMA may
request access to the PCI bus sooner if the amount of data available in the
FIFO exceeds the space remaining in the current host memory buffer or a
complete packet resides in the FIFO. Max value of n is 0xf.
1394a PCI PHY/Link Open Host Controller
Description
FW322 06 T100
69