l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet - Page 52

• Manufacturer Part Number: l-fw32206t100
• Description: 1394a Phy/link Open Host Controller
• Manufacturer: ETC-unknow

FW322 06 T100
1394a PCI PHY/Link Open Host Controller
Internal Registers
Isochronous Transmit Interrupt Event (isoXmitIntMask) Register
The Isochronous Transmit Interrupt Event (isoXmitIntMask) set/clear register reflects the interrupt state of the iso-
chronous transmit contexts. An interrupt is generated on behalf of an isochronous transmit context if an
OUTPUT_LAST command completes and its interrupt bits are set. Upon determining that the Interrupt Event regis-
ter isochTx (bit 6) (see Table 39) interrupt has occurred, software can check this register to determine which con-
text(s) caused the interrupt. The interrupt bits are set by an asserting edge of the corresponding interrupt signal, or
by writing a 1 in the corresponding bit in the set register. The only mechanism to clear the bits in this register is to
write a 1 to the corresponding bit in the clear register.
Reading the isoXmitIntEventSet register returns the current state of the isoXmitIntEvent register. Reading the
isoXmitIntEventClear register returns the masked version of the isoXmitIntEvent register, i.e., the bit-wise AND
function of isoXmitIntEvent and isoXmitIntMask.
Offset:
Default:
Reference:
Table 41. Isochronous Transmit Interrupt Event Register Description
52
52
31:8
Bit
7
6
5
4
3
2
1
0
Field Name
Reserved
isoXmit7
isoXmit6
isoXmit5
isoXmit4
isoXmit3
isoXmit2
isoXmit1
isoXmit0
90h
94h
0000 00XXh
1394 Open Host Controller Specification, Rev. 1.1, Section 6.3
RSCU Isochronous transmit channel 7 caused the interrupt event register bit 6 (isochTx)
RSCU Isochronous transmit channel 6 caused the interrupt event register bit 6 (isochTx)
RSCU Isochronous transmit channel 5 caused the interrupt event register bit 6 (isochTx)
RSCU Isochronous transmit channel 4 caused the interrupt event register bit 6 (isochTx)
RSCU Isochronous transmit channel 3 caused the interrupt event register bit 6 (isochTx)
RSCU Isochronous transmit channel 2 caused the interrupt event register bit 6 (isochTx)
RSCU Isochronous transmit channel 1 caused the interrupt event register bit 6 (isochTx)
RSCU Isochronous transmit channel 0 caused the interrupt event register bit 6 (isochTx)
Type
R
(continued)
Reserved. Bits 31:8 return 0s when read.
interrupt.
interrupt.
interrupt.
interrupt.
interrupt.
interrupt.
interrupt.
interrupt.
set register
clear register
Description
Data Sheet, Rev. 1
December 2005
Agere Systems Inc.