l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet - Page 8

• Manufacturer Part Number: l-fw32206t100
• Description: 1394a Phy/link Open Host Controller
• Manufacturer: ETC-unknow

FW322 06 T100
1394a PCI PHY/Link Open Host Controller
FW322 Functional Description
OHCI Data Transfer
The OHCI core consists of the three blocks shown in Figure 3: the PCI interface (PCI32_interface), the isochro-
nous data transfer, and the asynchronous data transfer blocks. The PCI interface provides an interface between
the OHCI blocks and the PCI core. It contains an arbiter to select the appropriate OHCI data engine to gain access
to the PCI core. In addition, the PCI interface includes a register select function to decode slave accesses to the
OHCI core and select data from appropriate sources. The PCI interface also has an OHCI interrupt handler to ser-
vice OHCI generated interrupts, which are ultimately translated into PCI interrupts.
OHCI Isochronous Data Transfer
The isochronous data transfer logic, which is incorporated into the OHCI core, handles the transfer of isochronous
data between the link core and the PCI interface module. It consists of the Isochronous register access module, the
isochronous transmit DMA module, the isochronous receive DMA module, the isochronous transmit (IT) FIFO, and
the isochronous receive (IR) FIFO.
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PCI SLAVE
PCI MASTER
PCI32 INTERFACE
INTERRUPT
REGISTER
HANDLER
ARBITER
SELECT
OHCI
Figure 3. OHCI Core Block Diagram
(continued)
ASYNCHRONOUS DATA TRANSFER
REGISTER
ACCESS
ASYNC
ISOCHRONOUS DATA TRANSFER
REGISTER
ACCESS
ISOCH
SELFID DMA
ASYNC_RX
RESPONSE
ASYNC_TX
REQUEST/
PHYSICAL
DMA
DMA
DMA
TRANSMIT
RECEIVE
ISOCH
ISOCH
DMA
DMA
Data Sheet, Rev. 1
ASYNC
ASYNC
ADMIN
ADMIN
December 2005
Agere Systems Inc.
RX
TX
AR FIFO
AT FIFO
IR FIFO
IT FIFO