l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet - Page 68

• Manufacturer Part Number: l-fw32206t100
• Description: 1394a Phy/link Open Host Controller
• Manufacturer: ETC-unknow

FW322 06 T100
1394a PCI PHY/Link Open Host Controller
Internal Registers
FW322 Vendor-Specific Registers
The FW322 contains a number of vendor-defined registers used for diagnostics and control of low-level hardware
functionality. These registers are addressable in the upper 2K of the 4K region defined by PCI Base Address
register 0 (registers defined by the OHCI specification reside in the lower 2K of this region). These registers are
also programmable via the serial EEPROM. These control registers should not be changed when the link is
enabled.
Table 60. FW322 Vendor-Specific Registers Description
Isochronous DMA Control
The fields in this register control when the isochronous DMA engines access the PCI bus and how much data they
will attempt to move in a single PCI transaction. The actual PCI burst sizes will also be affected by 1394 packet size,
host memory buffer size, FIFO constraints, and the PCI cache line size.
Offset:
Default:
Table 61. Isochronous DMA Control Registers Description
68
68
12’h800
12’h808
12’h840
Offset
15:12
Bits
11:8
7:4
3:0
IR Maximum Burst The maximum number of quadlets that will be written by the IR DMA in
Register Name
IT Maximum Burst The maximum number of quadlets that will be fetched by the IT DMA in
AsyDMACtrl
LinkOptions
IsoDMACtrl
IT Threshold
IR Threshold
800h
0000 7373h
Field
(continued)
Controls PCI access for the isochronous DMA engines. Initial values
are loaded from serial EEPROM, if present (see Table 61 of this data
sheet).
Controls PCI access and AT FIFO threshold for the asynchronous DMA
engines. Initial values are loaded from serial EEPROM, if present (see
Table 62 of this data sheet).
Controls low-level functionality of the link core. Initial values are loaded
from serial EEPROM, if present (see Table 63 of this data sheet).
one PCI transaction. The maximum burst is 16 * (n + 1) quadlets;
n defaults to 7 (128 quadlets). Max value of n is 0xf.
This field defines the amount of available space that is needed in the IT
FIFO, before the IT DMA will request access to the PCI bus. The
threshold is 16 * (n + 1) quadlets; n defaults to 3 (64 quadlets). Note,
however, that the IT DMA may request access to the PCI bus sooner if
the amount of data to be fetched from memory is less than the amount
of space available in the IT FIFO. Max value of n is 0xf.
one PCI transaction. The maximum burst is 16 * (n + 1) quadlets;
n defaults to 7 (128 quadlets). Max value of n is 0xf.
This field defines the amount of available data that is needed in the IR
FIFO, before the IR DMA will request access to the PCI bus. The
threshold is 16 * (n + 1) quadlets; n defaults to 0 (16 quadlets). Note,
however, that the IR DMA may request access to the PCI bus sooner if
the amount of data available in the FIFO exceeds the space remaining
in the current host memory buffer or a complete packet resides in the
FIFO. Max value of n is 0xf.
Description
Description
Data Sheet, Rev. 1
December 2005
Agere Systems Inc.