l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet - Page 33

• Manufacturer Part Number: l-fw32206t100
• Description: 1394a Phy/link Open Host Controller
• Manufacturer: ETC-unknow

Data Sheet, Rev. 1
December 2005
Internal Registers
OHCI Registers
The OHCI registers defined by the 1394 Open Host Controller Interface Specification are memory mapped into a
2 Kbyte region of memory pointed to by the OHCI Base Address register located at offset 10h in PCI configuration
space. These registers are the primary interface for controlling the FW322 IEEE 1394 OHCI function. This section
provides a summary of the registers within this interface and a description of the individual bit fields within each
register. For more details regarding these registers and bits, please refer to the 1394 Open Host Controller Inter-
face Specification, Rev. 1.1.
In addition to regular read/write registers, there are several pairs of set and clear registers implemented within the
OHCI register interface. For each pair of set and clear registers, there are two addresses that correspond to indi-
vidual set/clear registers: RegisterSet and RegisterClear. Refer to Table 18 for a listing of these registers. A 1 bit
written to RegisterSet causes the corresponding bit in the register to be set, while a 0 bit leaves the corresponding
bit unaffected. A 1 bit written to RegisterClear causes the corresponding bit in the register to be reset, while a 0 bit
leaves the corresponding bit unaffected. Typically, a read from either RegisterSet or RegisterClear returns the con-
tents of the set or clear register. However, in some instances, reading the RegisterClear provides a masked version
of the set or clear register. The Interrupt Event register is an example of this behavior.
The following FW322 OHCI register definitions are based on version 1.1 of the 1394 Open Host Controller
Specification.
Table 18. OHCI Register Map
Agere Systems Inc.
Context
DMA
—
Asynchronous Transmit Retries
Configuration ROM Header
Posted Write Address High
Posted Write Address Low
Configuration ROM Map
Global Unique ID ROM
Host Controller Control
Global Unique ID High
Global Unique ID Low
Vendor Identification
CSR Compare Data
Bus Identification
Register Name
(continued)
OHCI Version
CSR Control
Bus Options
CSR Data
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PostedWriteAddressLo
PostedWriteAddressHi
CSRCompareData
1394a PCI PHY/Link Open Host Controller
ConfigROMmap
HCControlClear
ConfigROMhdr
HCControlSet
Abbreviation
GUID_ROM
CSRControl
BusOptions
ATRetries
CSRData
VendorID
GUIDLo
GUIDHi
Version
BusID
—
—
—
—
—
—
Reserved
Offset
1Ch
0Ch
2Ch
3Ch
5Ch
00h
04h
08h
10h
14h
18h
20h
24h
28h
30h
34h
38h
40h
50h
54h
58h
60h
FW322 06 T100
Specification
Reference
13.2.8.1
OHCI
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
5.5.6
5.2
5.3
5.4
5.6
5.7
—
—
—
—
—
—
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