l-fw32206t100 ETC-unknow, l-fw32206t100 Datasheet - Page 67

• Manufacturer Part Number: l-fw32206t100
• Description: 1394a Phy/link Open Host Controller
• Manufacturer: ETC-unknow

Data Sheet, Rev. 1
December 2005
Internal Registers
Isochronous Receive Context Match (IR DMA ContextMatch) Register
The Isochronous Receive Context Match register is used to control on which isochronous cycle the context should
start. The register is also used to control which packets are accepted by the context.
Offset:
Default:
Reference:
Table 59. Isochronous Receive Context Match Register Description
Agere Systems Inc.
26:12
11:8
5:0
Bit
31
30
29
28
27
7
6
channelNumber
tag1SyncFilter
Field Name
cycleMatch
XXXX XXXXh
1394 Open Host Controller Specification, Rev. 1.1, Section 10.3. 3.
Reserved
Reserved
410Ch + (32 * n)
sync
tag3
tag2
tag1
tag0
(continued)
Type
RW
RW
RW
RW
RW
RW
RW
RW
R
R
If this bit is set, then this context matches on iso receive packets with a
tag field of 11b.
If this bit is set, then this context matches on iso receive packets with a
tag field of 10b.
If this bit is set, then this context matches on iso receive packets with a
tag field of 01b.
If this bit is set, then this context matches on iso receive packets with a
tag field of 00b.
Reserved. Bit 27 returns a 0 when read.
Contains a 15-bit value, corresponding to the low-order 2 bits of cycle-
Seconds and the 13-bit cycleCount field in the cycleStart packet. If Iso-
chronous Receive Context Control register bit 29 (cycleMatchEnable)
is set, then this context is enabled for receives when the 2 low-order
bits of the Bus Isochronous Cycle Timer register cycleSeconds field
(bits 31:25) and cycleCount field (bits 24:12) value equal this field’s
(cycleMatch) value.
This field contains the 4-bit field, which is compared to the sync field of
each isochronous packet for this channel when the command descrip-
tor’s w field is set to 11b.
Reserved. Bit 7 returns 0 when read.
If this bit and bit 29 (tag1) are set, then packets with tag2’b01 are
accepted into the context if the two most significant bits of the packets
sync field are 00b. Packets with tag values other than 01b are filtered
according to tag0, tag2, and tag3 (bits 28, 30, and 31, respectively)
without any additional restrictions. If this bit is cleared, then this context
matches on isochronous receive packets as specified in bits 28:31
(tag0:tag3) with no additional restrictions. If the tag1SyncFilterLock bit
of the Link Control register is set, then this bit is read only and is set to
one by the OHCI.
This 6-bit field indicates the isochronous channel number for which this
isochronous receive DMA context accepts packets.
1394a PCI PHY/Link Open Host Controller
Description
FW322 06 T100
67