DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 195

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.1.5
ODR is a register that stores output data for ports. The upper two bits in PHODR are reserved.
7.1.6
NCE enables or disables the noise cancel circuit at port n pins in bit units.
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
Bit Name
Pn7ODR
Pn6ODR
Pn5ODR
Pn4ODR
Pn3ODR
Pn2ODR
Pn1ODR
Pn0ODR
Bit Name
Pn7NCE
Pn6NCE
Pn5NCE
Pn4NCE
Pn3NCE
Pn2NCE
Pn1NCE
Pn0NCE
Output Data Register (PnODR) (n = A to D and F to J)
Noise Canceller Enable Register (PnNCE) (n = 6, C, and G)
Initial Value
0
0
0
0
0
0
0
0
Initial Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
ODR stores the output data for the pins that are
used as the general output port.
Description
Noise cancel circuit is enabled when a bit in this
register is set to 1, and the pin setting state is
fetched in P6DR or PnPIN in the sampling cycle
set by the PnNCCS.
Rev. 3.00 Sep. 28, 2009 Page 149 of 910
Section 7 I/O Ports
REJ09B0350-0300