DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 380

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 12 16-Bit Duty Period Measurement Timer (TDP)
12.3.2
TDPWDMX is a 16-bit readable/writable register. When the TDPMDS bit in TDPCR1 is cleared
(timer mode), TDPWDMX is available as a compare match register. When the TDPMDS bit in
TDPCR1 is set to 1 (cycle measurement mode), TDPWDMX is available as a pulse width upper
limit register.
In timer mode, the TDPWDMX value is continually compared with the TDPCNT value. If the
values match, the CMF flag in TDPCSR is set to 1. Note, however, that comparison is disabled in
the second half of a write cycle to TDPWDMX.
In cycle measurement mode, TDPWDMX can be used to set the upper limit value of the
measurement pulse width. When the second edge (the second edge of this period) of the
measurement period is detected, the TDPCNT value is transferred to TDPICR and the values of
TDPICR and TDPWDMX are compared. If the TDPICR value is greater than the TDPWDMX
value, the TWDMXOVF flag in TDPCSR is set to 1. TDPWDMX must always be accessed in 16-
bit units and cannot be accessed in 8-bit units. TDPWDMX is initialized to H'FFFF.
12.3.3
TDPWDMN is a 16-bit readable/writable register. When the TDPMDS bit in TDPCR1 is set to 1
(cycle measurement mode), TDPWDMN is available as a pulse width lower limit register.
In cycle measurement mode, TDPWDMN can be used to set the lower limit value of measurement
pulse width. When the second edge (the second edge of this period) of the measurement period is
detected, the TDPCNT value is transferred to TDPICR and the values of TDPICR and
TDPWDMN are compared. If the TDPICR value is less than the TDPWDMN value, the
TWDMNUDF flag in TDPCSR is set to 1. TDPWDMN must always be accessed in 16-bit units
and cannot be accessed in 8-bit units. TDPWDMN is initialized to H'0000.
12.3.4
TDPPDMX is a 16-bit readable/writable register. When the TDPMDS bit in TDPCR1 is set to 1
(cycle measurement mode), TDPPDMX is available as a cycle upper limit register.
In cycle measurement mode, TDPPDMX can be used to set the upper limit value of measurement
period. When the third edge (the first edge of the next period) of the measurement period is
detected, the TDPCNT value is transferred to TDPICR and the values of TDPICR and TDPPDMX
are compared. If the TDPICR value is greater than the TDPPDMX value, the TPDMXOVF flag in
Rev. 3.00 Sep. 28, 2009 Page 334 of 910
REJ09B0350-0300
TDP Pulse Width Upper Limit Register (TDPWDMX)
TDP Pulse Width Lower Limit Register (TDPWDMN)
TDP Cycle Upper Limit Register (TDPPDMX)