DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 589

IC H8S/2117 MCU FLASH 145TFLGA

DF2117VLP20V

Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VLP20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
(master output)
(master output)
(slave output)
User processing
ICDRF
ICDRR
SCL
SDA
SDA
IRTR
IRIC
(master output)
(master output)
(slave output)
User processing
Master transmit mode
ICDRR
ICDRF
SCL
SDA
SDA
IRTR
IRIC
Figure 17.11 Example of Operation Timing in Master Receive Mode
Figure 17.12 Example of Stop Condition Issuance Operation Timing
Bit 1
Data 1
Data 2
7
[4] IRIC clear
Bit 0
A
9
8
[1] TRS=0 clear
[6] Set ACKB = 1
A
9
[3]
SCL is fixed low until ICDR is read
in Master Receive Mode (MLS = WAIT = 0)
SCL is fixed low until ICDR is read
Master receive mode
[1] IRIC clear
Bit 7
1
[7] ICDR read
(Data 2)
Bit 7
Bit 6
1
2
(MLS = WAIT = 0)
Bit 6
Bit 5
2
3
[2] ICDR read
Data 1
Undefined value
(Dummy read)
Bit 5
Bit 4
3
Data 2
Data 3
4
Bit 4
Bit 3
4
5
Bit 3
Bit 2
5
6
Bit 2
Bit 1
6
7
[4] IRIC clear
Rev. 3.00 Sep. 28, 2009 Page 543 of 910
Bit 1
Bit 0
SCL is fixed low until
stop condition is issued
7
[9] IRIC clear
8
Bit 0
[3]
A
8
Section 17 I
9
SCL is fixed low until ICDR is read
[11] Set BBSY=0 and
(Stop condition instruction issuance)
A
[8]
9
SCP=0
[5] ICDR read
(Data 1)
Data 1
2
Stop condition generation
C Bus Interface (IIC)
Bit 7
[10] ICDR read
REJ09B0350-0300
1
Data 2
(Data 3)
Bit 6
2
Data 3

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