DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 672

IC H8S/2117 MCU FLASH 145TFLGA

DF2117VLP20V

Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VLP20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 19 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 626 of 910
REJ09B0350-0300
Bit
3
2
IRQ11E2 0
IRQ10E2 0
Bit Name Initial Value Slave Host Description
R/W
R/W
R/W
Host IRQ11 Interrupt Enable 2
Enables or disables an HIRQ11 interrupt request
when OBF2 is set by an ODR2 write.
0: HIRQ11 interrupt request by OBF2 and
[Clearing conditions]
1: [When IEDIR2 = 0]
[Setting condition]
Writing 1 after reading IRQ11E2 = 0
Host IRQ10 Interrupt Enable 2
Enables or disables an HIRQ10 interrupt request
when OBF2 is set by an ODR2 write.
0: HIRQ10 interrupt request by OBF2 and
[Clearing conditions]
1: [When IEDIR2 = 0]
[Setting condition]
Writing 1 after reading IRQ10E2 = 0
IRQE11E2 is disabled
Writing 0 to IRQ11E2
LPC hardware reset, LPC software reset
Clearing OBF2 to 0 (when IEDIR2 = 0)
HIRQ11 interrupt request by setting OBF2 to 1 is
enabled
[When IEDIR2 = 1]
HIRQ11 interrupt is requested
IRQE10E2 is disabled
Writing 0 to IRQ10E2
LPC hardware reset, LPC software reset
Clearing OBF2 to 0 (when IEDIR2 = 0)
HIRQ10 interrupt request by setting OBF2 to 1 is
enabled
[When IEDIR2 = 1]
HIRQ10 interrupt is requested

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