DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 688

IC H8S/2117 MCU FLASH 145TFLGA

DF2117VLP20V

Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VLP20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 19 LPC Interface (LPC)
Table 19.6 shows the scope of the LPC interface pin shutdown.
Table 19.6 Scope of LPC Interface Pin Shutdown
[Legend]
O:
Δ:
X:
In the LPC shutdown state, the LPC's internal state and some register bits are initialized. The order
of priority of LPC shutdown and reset states is as follows.
1. System reset (reset by RES pin input, or WDT overflow)
2. LPC hardware reset (reset by LRESET pin input)
3. LPC software reset (reset by LRSTB)
4. LPC hardware shutdown
5. LPC software shutdown
The scope of the initialization in each mode is shown in table 19.7.
Rev. 3.00 Sep. 28, 2009 Page 642 of 910
REJ09B0350-0300
Abbreviation
LAD3 to LAD0
LFRAME
LRESET
LCLK
SERIRQ
LSCI
LSMI
PME
GA20
CLKRUN
LPCPD
All register bits, including bits LPC4E to LPC1E, are initialized.
LRSTB, SDWNE, and SDWNB bits are cleared to 0.
SDWNE and SDWNB bits are cleared to 0.
SDWNB bit is cleared to 0.
Pin that is shutdown by the shutdown function
Pin that is shutdown only when the LPC function is selected by register setting
Pin that is not shutdown
Port
P33 to P30
P34
P35
P36
PB1
PB0
P80
P81
P82
P83
P37
Scope of
Shutdown
O
O
X
O
O
Δ
Δ
Δ
Δ
O
X
I/O
I/O
Input
Input
Input
I/O
I/O
I/O
I/O
I/O
Input
Input
Notes
Hi-Z
Hi-Z
LPC hardware reset function is active
Hi-Z
Hi-Z
Hi-Z, only when LSCIE = 1
Hi-Z, only when LSMIE = 1
Hi-Z, only when PMEE = 1
Hi-Z, only when FGA20E = 1
Hi-Z
Needed to clear shutdown state

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